Session two
Upcoming SlideShare
Loading in...5
×
 

Session two

on

  • 576 views

 

Statistics

Views

Total Views
576
Views on SlideShare
534
Embed Views
42

Actions

Likes
0
Downloads
44
Comments
0

3 Embeds 42

http://www.weebly.com 33
http://startgroup.weebly.com 8
http://startgroup.dinstudio.com 1

Accessibility

Categories

Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Session two Session two Presentation Transcript

    • http://www.bized.co.uk Session 2Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukRefresh Your Memory Session-2 2 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukRefresh Your Memory Answer library IEEE; USE ieee.std_logic_1164.all; Entity AND_GATE is Port ( X1 : in std_logic_vector(4 downto 0 ); X2 : in std_logic_vector(4 downto 0 ); Y : out std_logic_vector(4 downto 0 ) ); END AND_GATE; Architecture Behave of AND_GATE IS begin Y <= X1 AND X2 ; END Behave ; 3 Copyright 2006 – Biz/ed
    • http://www.bized.co.uk 2 - Demo no. 2 SPARTON_3 FPGA starter boardContents - Combinational vs Sequential -Data Objects -Signals -VHDL Statements -Sequential Statements -What is Process -IF Statement -CASE Statement -Combinational Logic -Sequential Logic 4 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukXilinx Spartan 3-FPGA Starter Board 5 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk 6 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukCombinational Vs. Sequential logic circuit in any digital system we can divide the circuits into two types : Combinational logic circuits implement Boolean functions, so the output in this circuits is function only on their inputs, and are not based on clocks. Sequential circuits compute their output based on input and state, and that the state is updated based on a clock. 7 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukSignals Signals used to connect between systems or connect components inside systems Types of signals --External Signals -In,Out ports -Internal connections in structuraldiscussed later --Internal Signals -connect devices inside the block -used for Intermediate calculations Note We use Internal Signals for: Avoid illegal port usage situations like Read Output port 8 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukSignalsSignal declaration architecture <arch_name> of <entity_name> is -- architecture declarations signal <sig_name> : <sig_type>; . . . begin <Architecture body> End <arch_name> ; 9 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• NAND GateA C DB Example 5 10 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukNAND Gate LIBRARY ieee; USE ieee.std_logic_1164.all; A ENTITY NAND_GATE IS C D port ( A : in STD_LOGIC; B : in STD_LOGIC; B D : out STD_LOGIC ); END ENTITY NAND_GATE ; ARCHITECTURE behave OF NAND_GATE IS SIGNAL C : std_logic; BEGIN C <= A and B ; D <= not C ; END behave; 11 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• Write the VHDL code for this logic circuitA DB Exercise 1CD F 12 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukWrite the VHDL code for this logic circuit A LIBRARY ieee; USE ieee.std_logic_1164.all; SIG_1 G B ENTITY NAND_GATE IS port ( A,B,C,D : in STD_LOGIC; G,F : out STD_LOGIC ); END ENTITY NAND_GATE ; C SIG_2 ARCHITECTURE behave OF NAND_GATE IS SIGNAL SIG_1 : std_logic; F SIGNAL SIG_2 : std_logic; D BEGIN SIG_1 <= A and B ; SIG_2 <= SIG_1 and C ; F <= SIG_2 and D ; G <= SIG_1 ; END behave; 13 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk•VHDL has concurrent statements and sequential statements•Concurrent statements are executed in parallel w.r.t each other. With – select When – else Process statement Assign statement•Sequential statements are executed in sequence w.r.t each other. Statements•Sequential statements should be written inside a “process” If statement loop statement Case statement Wait and Null statement 14 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukProcess-What is a Process Process allows writing sequential statements within concurrent environment Process is like a container that include the sequential statementsProcess declarationprocess (sensitivity list)begin sequential statements ;end process ;Note<sensitivity_list>: List of signals/ports that cause the process to be executed whenever there is achange in their values 15 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukProcess Architecture behave of comb_ct is Begin process (x,y) begin z <= x and y; h <= x or y; t <= x xor y; … end process; End behave ; Statements inside a “process” are read sequentially and executed when the process suspends (“end process” is reached) very important note: What is this statement differs from z<= x and y; 16 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukQuestion Statements shown at left are inside a process and at right are outside it what is the result in the two cases Process () begin A <= B ; A <= B ; A <= C ; A <= C ; end 17 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukQuestion Statements shown at left are inside a process and at right are outside it what is the result in the two cases Architecture Architecture Process () begin begin A <= B ; A <= B ; A <= C ; A <= C ; end end end B B A A C A C 18 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukQuestion Statements shown at left are inside a process and at right are outside it what is the result in the two cases Process () begin A <= B ; A <= B ; B <= A ; B <= A ; end 19 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukIF Statement Executes a list of sequential statements when the corresponding condition evaluates to true V.IMPORTANT ROLE The branches order is important as they imply a priority Syntax If <condition> then -- list of sequential statements elsif <condition> then -- list of sequential statements else -- list of sequential statements end if; <condition> Boolean expression that evaluates to either TRUE or FALSE 20 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• Adder/Subtractor A Result B Adder_Subtractor Example 6 Operation Operation =1  a+b Operation =0  a-b 21 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukAdder/Subtractor LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY add_sub IS port ( a, b : in integer; result : out integer; operation : in std_logic); -- add or subtract END ENTITY add_sub; ARCHITECTURE behave OF add_sub IS BEGIN process ( a, b, operation What is sensitivity list !! ) begin if (operation = 1) then -- Add when operation = 1 result <= a + b; else -- Subtract otherwise result <= a - b; end if; end process; END ARCHITECTURE behave; 22 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukAdder/Subtractor LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY add_sub IS port ( a, b : in integer; result : out integer; operation : in std_logic); -- add or subtract END ENTITY add_sub; ARCHITECTURE behave OF add_sub IS BEGIN process ( a, b, operation ) begin if (operation = 1) then -- Add when operation = 1 result <= a + b; else -- Subtract otherwise result <= a - b; end if; end process; END ARCHITECTURE behave; 23 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• Simple Comparator A C B Comparator Example 7 A=B C=“00” A>B C=“01” A<B C=“10” 24 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukSimple ComparatorLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY comparator IS port( a, b : in std_logic_vector(7 downto 0); c : out std_logic_vector(1 downto 0); );END ENTITY;ARCHITECTURE behave OF comparator ISBEGIN process (a, b) begin if (A = B ) then -- equality c <= "00"; elsif (A > B) then -- greater than c <= "01"; elsif (A < B) then -- greater than c <= "10"; else -- covers other cases c <= “ZZ"; end if; end process;END ARCHITECTURE; 25 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukCASE StatementMakes several conditions on the same signalSyntax case <expression> is when <choice> => -- list of sequential statements when <choice> => -- list of sequential statements when others => -- list of sequential statements end case; 26 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukCASE Statement<expression> can be a signal or a variable (discussed later)<choice> constants representing one of possible <expression> values.V.IMPORTANT ROLE-“When others” is a must if not all values of <expression> are covered-Each branch of a Case statement can have any number of sequential statements 27 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• 4 x 1 Multiplexer Example 8 28 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk4 x 1 Multiplexer Architecture rtl of mux_case is begin process (a,b,c,d,sel) begin Case sel is When "00" => f <= a; When "01" => f <= b; Do we need all these signals? On sensitivity list ?? When "10" => f <= c; When "11" => f <= d; when others => -- is "when others" a must? f <= „Z‟; End case; End process; End architecture; 29 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• Simulate 2 x 4 Decoder on Modelsim lab 1 30 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk2 x 4 Decoder Architecture rtl of dec is begin process (a) begin Case a is When "00" => f <= “0001”; When "01" => f <= “0010”; When "10" => f <= “0100”; When "11" => f <= “1000”; when others => f <= “ZZZZ”; End case; End process; End rtl ; How to make 4 x 2 Encoder ! 31 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk 1-Area OptimizationDuring writing a code for implementation you must save your resourcesExample Write a code describing this Adder OpSel Function 00 A+B 01 C+D 10 E+F 11 G+HNote that the selector can select one addition at a time, the operators are mutuallyexclusive 32 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukIt is better to write a code that describe the circuit on the right as adders take much biggerarea than multiplexershis transformation of operators is called Resource Sharing 33 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukPossible solutions Solution 1process (OpSel,A,B,C,D,E,F,G,H)begin case OpSel is when "00" => Z <= A + B ; when "01" => Z <= C + D ; when "10" => Z <= E + F ; when "11" => Z <= G + H ; when others => Z <= (others => X) ; end case ;end process ;Here the code is Tool Driven Resource Sharing, the tool understand that we don’t need tomake four adders and one Adder is implemented.General NoteTo ensure resource sharing, operators must be coded in the same process, and same code(case or if) structure. 34 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk Solution 2X <= Mux4(OpSel, A, C, E, G) ;Y <= Mux4(OpSel, B, D, F, H) ;Z <= X + Y ;Here the code is Code Driven Resource Sharing, You forced the tool to use only one Adder. Solution 3Process (OpSel, A, B, C, D, E, F, G, H)begin if (OpSel = "00") then Z <= A + B; end if; if (OpSel = "01") then Z <= C + D; end if; if (OpSel = "10") then Z <= E + F; end if; if (OpSel = "11") then Z <= G + H; end if;end process ;Bad Code that may defeat Resource Sharing.Synthesis tool may create a separate resource for each adder. Don’t do that! 35 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukSequential Circuits Clock periodA digital clock signal is a square wave voltage.In complex circuits a clock with a fixed frequency is used for timing.To store and pass the data or digital signals through, some specific gates are used whichare called latches or flip-flops. These are some kind of memory that store their input overtheir output by a specific level or edge of the clock.Asynchronous Operation don’t wait clockSynchronous wait clock to get an input and to produce an output 36 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukD-Flip Flop D QReset Clk Enable Q+ Reset D_FF 1 - - 0 0 No rising_edge - Q enable 0 Rising_edge 0 Q 0 Rising_edge 1 D clkAsynchronous resetSynchronous enable Clock period 37 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• Simple D-Flip Flop D Q D_FF Example 9 clk 38 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukSimple D-FF Library ieee; use ieee.std_logic_1164.all; Entity d_ff is Port( D, clk : in std_logic; Q : out std_logic ); end entity; Architecture behav of d_ff is Begin process(clk) begin rising_edge() : defined for std_logic type if rising_edge(clk) then Q <= D; end if; end process; end behav; 39 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• D-FF with Asynchronous reset D Q Reset D_FF Example 10 clk 40 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukD-FF with Asynchronous reset Library ieee; use ieee.std_logic_1164.all; Entity d_ff is Port( d, clk, rst : in std_logic; Q : out std_logic); end entity; Architecture behav of d_ff is Begin process(clk, rst) begin If (rst = 1) then Since rst has higher priority over the clk edge Q <= 0; We put it on sensitivity list elsif rising_edge(clk) then Q <= d; We have now a D Flip Flop with asynchronous end if; reset end process; end behav; 41 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• D-FF with Asynchronous reset and Synchronous enable D Q Reset D_FF Example enable 11 clk 42 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukD-FF with Asynchronous reset and Synchronous enable Library ieee; use ieee.std_logic_1164.all; Reset Clk Enable Q+ Entity d_ff is 1 - - 0 Port( d, clk, rst,en : in std_logic; Q : out std_logic 0 No rising_edge - Q ); 0 Rising_edge 0 Q end entity; 0 Rising_edge 1 D Architecture behav of d_ff is Begin process(clk, rst) begin If (rst = 1) then Enable has lower priority w.r.t the clk edge Q <= 0; So we don’t put it in sensitivity list as it will slow the elsif rising_edge(clk) then simulation If (en = 1) then Q <= d; end if; We have now a D Flip Flop with asynchronous end if; reset and synchronous enable end process; end behav; 43 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukD-Latch vs D-Flip FlopWith a latch, a signal can’t propagate through until the clock is high .With a Flip-flop, the signal only propagates through on the rising edge. 44 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.uk• D_Latch (positive level) D Q Reset D_FF Example enable 12 clk 45 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukD-Latch with Asynchronous reset and Synchronous enable library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity d_ff is port( clk,reset,enable: in std_logic; d: in std_logic; q: out std_logic); end d_ff; architecture Behavioral of d_ff is begin process(clk,reset,d) begin if reset = 1 then q<= 0; elsif clk = 1 then if enable = 1 then q<= d; end if; end if; end process; end Behavioral; 46 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukAssignment Session-2Write a code describing a T-Flip Flop TIf the T input is high, the T flip-flop changes Qstate ("toggles") whenever the clock input isstored. If the T input is low, the flip-flop holds Reset D_FFthe previous value. Q’ clk 47 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukMini Project-1 48 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukALU Arithmetic Logic UnitIt is a circuit capable of executing both kinds of operations, arithmetic as well aslogical.Its operation is described next slide as follow : The output (arithmetic or logical) is selected by the MSB of sel The specific operation is selected by sel’s other three bits. 49 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukSel Operation Function Unit0000 Y<= a Transfer A0001 Y<= a+1 Increment A0010 Y<= a-1 Decrement A0011 Y<= b Transfer B Athematic0100 Y<= b+1 Increment A0101 Y<= b-1 Decrement A0110 Y<= a+b Add a and b0111 Y<= a+b+cin Add a and b and carry1000 Y<= not a Complement a1001 Y<= not b Complement b1010 Y<= a AND b AND1011 Y<= a OR b OR logic1100 Y<= a NAND b NAND1101 Y<= a NOR b NOR1110 Y<= a XOR b XOR1111 Y<= a XNOR b XNOR 50 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukRequired -VHDL code of this ALU -Verify functionality using ModelsimDeadline -Next session 51 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukDownload Session 2 material Session 2.pdf Modelsim tuotorial.pdf Xilinx ISE tuotorial.pdf lab1.txtAsk for the material through mail start.courses@gmail.comFacebook group start.group@groups.facebook.com 52 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukQuestions Session-2 53 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukTake Your Notes Print the slides and take your notes here--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 54 Copyright 2006 – Biz/ed
    • Session 2 http://www.bized.co.ukSee You Next Session 55 Copyright 2006 – Biz/ed