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# Session three

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### Session three

1. 1. http://www.bized.co.uk Session 3Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
2. 2. http://www.bized.co.uk 3 -ALU mini project discussionContents -Concurrent Statements 1-Assign Statement 2-Process 3-When-else 4-With-select -Data Objects 1-Signals 2-Variables 3-Constants 2 Copyright 2006 – Biz/ed
3. 3. Session 3 http://www.bized.co.uk Sel Operation 0000 Y<= aALU mini project discussion 0001 Y<= a+1 0010 Y<= a-1 0011 Y<= b 0100 Y<= b+1 0101 Y<= b-1 0110 Y<= a+b 0111 Y<= a+b+cin 1000 Y<= not a 1001 Y<= not b 1010 Y<= a AND b 1011 Y<= a OR b 1100 Y<= a NAND b 1101 Y<= a NOR b 1110 Y<= a XOR b 1111 Y<= a XNOR b 3 Copyright 2006 – Biz/ed
4. 4. Session 3 http://www.bized.co.uk Assignment Process Concurrent When-Else With-SelectStatements Concurrent IF Statements CASE Sequential FOR WAIT 4 Copyright 2006 – Biz/ed
5. 5. Session 3 http://www.bized.co.ukConcurrent Statements ConcurrencyWe can consider any system to be consisted of many blocks each has aspecific function and work together concurrently (in parallel) to form thewhole function.As VHDL is a Hardware Description Language so the default statements inVHDL are those who are executed in parallel.These statements are called Concurrent statements. 5 Copyright 2006 – Biz/ed
6. 6. Session 3 http://www.bized.co.ukConcurrent Statements Illustrating Example In this Example, the value of x depends on a AND b, whenever a/b changes x will change accordingly Similarly the value of y will always change whenever c/d changes It might happen that the value of x changes at the same time the value of y changes  Both changes happen concurrently a x b BEGIN e x <= a AND b; c y <= c AND d; y END ; e <= x AND y; dThese assignment statements are concurrent, they can be written in any order Think as Hardware 6 Copyright 2006 – Biz/ed
7. 7. Session 3 http://www.bized.co.ukConcurrent Statements 1- Assign StatementsAssignments relating outputs to inputsNon Blocking Assignment <= is usedAssign statements can be written in any order. architecture rtl of logic_gate is begin x <= a AND b; y <= c OR b; end rtl; 7 Copyright 2006 – Biz/ed
8. 8. Session 3 http://www.bized.co.ukConcurrent Statements 2- ProcessProcess allows writing sequential statements within concurrent environmentProcess declaration 1 2 3<Process Name> : PROCESS (sensitivity list) 4 process declaration; 5Begin sequential statements ; 6 7 1 <Process Name> : Optional LabelEnd PROCESS <Process Name> ; 2 PROCESS : Keyword 3 sensitivity list : Signals inside it when make an event, the process trigger 4 process declaration 5 Begin : Keyword 6 Sequential statements 7 End : Process Suspend 8 Copyright 2006 – Biz/ed
9. 9. Session 3 http://www.bized.co.ukConcurrent Statements TransactionsProcess (A,B)begin C <= A AND B ;end process ; A B C 0 1 0 1 0 0 1 1 1The current value of A,B is read and the process is begun .C <= A AND B ; causes a transactionThe value updated in C when the process suspend. Transaction occurs when the process suspend 9 Copyright 2006 – Biz/ed
10. 10. Session 3 http://www.bized.co.ukConcurrent Statements EventsProcess (A,B)begin C <= A AND B ;end process ; A B C 0 1 0 1 0 0 1 1 1If the value of D is changed as a result of this transaction, an event occurs on thissignal. Event occurs on signal when the value change 10 Copyright 2006 – Biz/ed
11. 11. Session 3 http://www.bized.co.ukConcurrent Statements Events vs Transactions All signal assignment cause a transaction to be scheduled, but not every transaction will result in an event on the target signal. Note Only an event on a given signal will cause a process to trigger if that signal is included in its sensitivity list. 1-Signal A =0 2-Signal B changes to 0 3-process triggers on signal B event 4-Expression reevaluated 5-Transaction scheduled logic 0 on C 6-Process suspend 7-Tranasction applied to C 8-Value of C does not changed 9-No event on C only Transaction 11 Copyright 2006 – Biz/ed
12. 12. Session 2 http://www.bized.co.uk• Find values of A,D and BProcess (A,B)begin A <= B + C ; D <= B + E ; B <= F + G ;end process ; Example Signal Value E 3 13 C 2 F 4 B 1 G 5 12 Copyright 2006 – Biz/ed
13. 13. Session 3 http://www.bized.co.ukProcess (A,B)begin A <= B + C ; D <= B + E ; B <= F + G ;end process ; Signal Value Signal After first After Event E 3 time this Process Process Suspend C 2 Trigger F 4 A 3 11 B 1 D 4 12 G 5 B 9 9 13 Copyright 2006 – Biz/ed
14. 14. Session 3 http://www.bized.co.ukConcurrent Statements Modeling Concurrency A VHDL simulator is event driven - At any single point of discrete simulation time: (1) All processes execute until they suspend (2) Signals are updated (3) Events on those signals cause more processes to resume execution This is referred to as a delta cycle 14 Copyright 2006 – Biz/ed
15. 15. Session 3 http://www.bized.co.ukConcurrent Statements Modeling ConcurrencyThe event scheduler is the heart of the HDL behavioral environmentEach transaction is scheduled at its appropriate discrete timeDiscrete time advances only when no more transactions are scheduled at the current time 15 Copyright 2006 – Biz/ed
16. 16. Session 3 http://www.bized.co.ukConcurrent Statements Connecting ProcessesProcesses and other concurrent operations are seen to take place at the same point indiscrete simulation time 16 Copyright 2006 – Biz/ed
17. 17. Session 3 http://www.bized.co.ukMultiple Processes 17 Copyright 2006 – Biz/ed
18. 18. Session 3 http://www.bized.co.ukConcurrent vs Sequential a suspended process is activated when any of signal of sensitivity list changes. If we have multiple process and all is activated then all statement is each process is executed sequentially . all process in any architecture are executed concurrently with each other. 18 Copyright 2006 – Biz/ed
19. 19. Session 3 http://www.bized.co.ukConcurrent Statements 3- when-else<target> <= <expression> when <condition> else <expression> when <condition> else <expression> when <condition> … else <expression> ;–LHS can be an internal signal or an output port–RHS is an expression that operates on internal signal and/or input ports when the branchcondition is true–Last “else” branch covers all missing conditions 19 Copyright 2006 – Biz/ed
20. 20. Session 3 http://www.bized.co.uk• 4X1 Multiplexer using when-else Example 14 20 Copyright 2006 – Biz/ed
21. 21. Session 3 http://www.bized.co.uk4X1 MUX (when-else)Architecture behave of mux_when isBegin F <= a when sel = "00" else b when sel = "01" else c when sel = "10" else d when sel = "11" else „Z‟;-- This is one statement with semicolon at the end onlyEnd behave ; 21 Copyright 2006 – Biz/ed
22. 22. Session 3 http://www.bized.co.ukConcurrent Statements 4- With – select - whenWith <select_signal> select <target> <= <expression> when <value>, <expression> when <value>, …. < expression> when others; –<select_signal> can be an internal signal or an input port –<target> can be an internal signal or an output port –<value> constants representing one of possible <select_signal> values. –“When others” is a must if not all values of <select_signal> are covered 22 Copyright 2006 – Biz/ed
23. 23. Session 3 http://www.bized.co.uk• 4X1 Multiplexer using with-select-when Example 15 23 Copyright 2006 – Biz/ed
24. 24. Session 3 http://www.bized.co.uk4X1 MUX (With – select - when)Architecture behave of mux_with isBegin With sel select F <= a when "00", b when "01", c when "10", d when "10", „Z‟ when others; -- needed to cover missing “sel” valuesEnd behave ; 24 Copyright 2006 – Biz/ed
25. 25. Session 3 http://www.bized.co.uk• Simulate 2X4 Decoder and 4X2 Encoder Using When-else and With-Select-When lab 2 25 Copyright 2006 – Biz/ed
26. 26. Session 3 http://www.bized.co.ukWith <select_signal> select <target> <= <expression> when <value>, <expression> when <value>, …. < expression> when others;------------------------------------------------------------------------------------<target> <= <expression> when <condition> else <expression> when <condition> else <expression> when <condition> … else <expression> ; 26 Copyright 2006 – Biz/ed
27. 27. Session 3 http://www.bized.co.uk2x4 Decoder (when-else)Architecture behave of decoder2x4 isBegin F <= "0001" when a = "00" else "0010" when a = "01" else "0100" when a = "10" else “1000" when a = "11" else “ZZZZ";End behave ; 27 Copyright 2006 – Biz/ed
28. 28. Session 3 http://www.bized.co.uk4X2 Encoder (when-else)Architecture behave of encoder2x4 isBegin F <= “00" when a = “1000" else "01" when a = “0100" else "10" when a = “0010" else "11" when a = “0001" else “ZZ";End behave ; 28 Copyright 2006 – Biz/ed
29. 29. Session 3 http://www.bized.co.uk2x4 Decoder (With – select - when) Architecture behave of decoder4x2 is Begin With a select F <= "0001" when "00", "0010" when "01", “0100" when "10", “1000" when "11", “ZZZZ" when others; End behave ; 29 Copyright 2006 – Biz/ed
30. 30. Session 3 http://www.bized.co.uk4X2 Encoder (With – select - when) Architecture behave of encoder2x4 is Begin with A select F <= "00" when “1000", "01" when "0100", "10" when “0010", "11" when “0001", “ZZ" when others; End behave ; 30 Copyright 2006 – Biz/ed
31. 31. Session 3 http://www.bized.co.ukQuestions Session-3 31 Copyright 2006 – Biz/ed
32. 32. http://www.bized.co.ukBreakBe ready for the second part of this session Start 1:00 1:01 1:02 1:03 1:04 1:05 1:06 1:07 1:08 1:09 1:10 1:12 1:13 1:14 1:15 1:16 1:17 1:18 1:19 1:20 1:21 1:22 1:23 1:24 1:25 1:26 1:27 1:28 1:29 1:30 1:31 1:32 1:33 1:34 1:35 1:36 1:37 1:38 1:39 1:40 1:41 1:42 1:43 1:44 1:45 1:46 1:47 1:48 1:49 1:50 1:51 1:52 1:53 1:54 1:55 1:56 1:57 1:58 1:59 2:00 0:01 0:02 0:03 0:04 0:05 0:06 0:07 0:08 0:09 0:10 0:12 0:13 0:14 0:15 0:16 0:17 0:18 0:19 0:20 0:21 0:22 0:23 0:24 0:25 0:26 0:27 0:28 0:29 0:30 0:31 0:32 0:33 0:34 0:35 0:36 0:37 0:38 0:39 0:40 0:41 0:42 0:43 0:44 0:45 0:46 0:47 0:48 0:49 0:50 0:51 0:52 0:53 0:54 0:55 0:56 0:57 0:58 0:59 1:11 0:11 32 Copyright 2006 – Biz/ed
33. 33. Session 3 http://www.bized.co.uk Data Objects 33 Copyright 2006 – Biz/ed
34. 34. Session 3 http://www.bized.co.ukData Objects -Data Objects are the Value holders -VHDL offers different data objects: 1-Signals Used to model connections Signals can be: External Signals Internal Signals 2-Variables Used for computations 3-Constants Used to store values that can’t be changed during simulation time 34 Copyright 2006 – Biz/ed
35. 35. Session 3 http://www.bized.co.ukData Objects 1-SignalsSignals Used to model connections, signals can be divided into two main types : External Signals (Ports) Used as an interface for the Entity to the outside world pass values in and out the circuit, between its internal units. Declared in Entity All PORTS of an ENTITY are signals by default Internal Signals Used inside the Architecture to connect different logic parts Declared in Architecture Represents circuit interconnects (wires) 35 Copyright 2006 – Biz/ed
36. 36. Session 3 http://www.bized.co.ukData Objects 1-SignalsExternal Signal declaration entity <entity_name> is Example port ( ENTITY AND_GATE IS <port_name> : <mode> <type>; port ( a,b : in BIT; ----- C : out BIT <port_name> : <mode> <type> ); ); END ENTITY AND_GATE ; End <entity_name> ; NAND_GATE ;Internal Signal declaration architecture <arch_name> of <entity_name> is -- architecture declarations signal <sig_name> : <sig_type>; begin Example End <arch_name> ; SIGNAL control: BIT ; SIGNAL y: STD_LOGIC_VECTOR(7 DOWNTO 0); 36 Copyright 2006 – Biz/ed
37. 37. Session 3 http://www.bized.co.ukData Objects 1-SignalsAssignment Operator Assigned using “<=” Non-Blocking AssignmentExample inp_x <=“0000”; sig_1 <=„1‟;BehaviorUsed in Concurrent or Sequential Outside a process its value is updated when their signal assignment is executed. Inside a process its value is updated after the process suspends only last assignment to signal listed inside the process is effective . 37 Copyright 2006 – Biz/ed
38. 38. Session 3 http://www.bized.co.ukObjective -Be familiar with signals declaration -Using Signals inside and outside the process Example 16 38 Copyright 2006 – Biz/ed
39. 39. Session 3 http://www.bized.co.ukA=1 ,B=1 ,C=1, D=2  C changes from 1 to 2What is the values of A,B and C ?Process (C,D)Begin A<=2; A= B<=A+C; A<=D+1; B= C<=B+A; C=End process; 39 Copyright 2006 – Biz/ed
40. 40. Session 3 http://www.bized.co.ukA=1 ,B=1 ,C=1, D=2  C changes from 1 to 2What is the values of A,B and C ?Process (C,D)Begin A<=2; A=3 B<=A+C; A<=D+1; B=3 C<=B+A; C=2End process; 40 Copyright 2006 – Biz/ed
41. 41. Session 3 http://www.bized.co.ukObjective -Be familiar with signals declaration -Using Signals inside and outside the process Exercise 2 41 Copyright 2006 – Biz/ed
42. 42. Session 3 http://www.bized.co.uksignal signal1: integer :=1; -- initial valuesignal signal2: integer :=2; -- initial valuesignal signal3: integer :=3; -- initial valuebeginprocess (………)begin …………… signal1 <= signal2; signal2 <= signal1 + signal3; signal3 <= signal2; RESULT <= signal1 + signal2 + signal3; ……………end process; Find the value of result? 42 Copyright 2006 – Biz/ed
43. 43. Session 3 http://www.bized.co.uk -- All Signals have the uninitialized value ‘U’ -- Force A = 1 then force A=0 then A=1library IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;entity signal_lab is port( A: in std_logic );End signal_lab;Architecture behave of signal_lab isSignal Z,G,F,X : STD_LOGIC;beginprocess (A)Begin A 1 0 1 Z <= A; G <= 1; Z ? ? ? F <= G; X <= F; G ? ? ? G <= 0; Z <= G; F ? ? ?end process ; X ? ? ?end behave; 43 Copyright 2006 – Biz/ed
44. 44. Session 3 http://www.bized.co.uk -- All Signals have the uninitialized value ‘U’ -- Force A = 1 then force A=0 then A=1library IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;entity signal_lab is port( A: in std_logic );End signal_lab;Architecture behave of signal_lab isSignal Z,G,F,X : STD_LOGIC;beginprocess (A)Begin A 1 0 1 Z <= A; G <= 1; Z U 0 0 F <= G; X <= F; G 0 0 0 G <= 0; Z <= G; F U 0 0end process ; X U U 0end behave; 44 Copyright 2006 – Biz/ed
45. 45. Session 3 http://www.bized.co.uk -- All Signals have the uninitialized value ‘U’ -- Force A = 1 then force A=0 then A=1library IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;entity signal_lab is port( A: in std_logic );End signal_lab;Architecture behave of signal_lab isSignal Z,G,F,X : STD_LOGIC;beginprocess (A)Begin Z <= A; G <= 1; F <= G; X <= F;end process ; G <= 0; Z <= G;end behave; 45 Copyright 2006 – Biz/ed
46. 46. Session 3 http://www.bized.co.uk -- All Signals have the uninitialized value ‘U’ -- Force A = 1 then force A=0 then A=1library IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;entity signal_lab is port( A: in std_logic );End signal_lab;Architecture behave of signal_lab isSignal Z,G,F,X : STD_LOGIC;beginprocess (A)Begin Any statement written out side Z <= A; G <= 1; process is concurrent statement , F <= G; It execute concurrently with process X <= F;end process ; G <= 0; G and Z has two values at same time Z <= G; value of A and value of G.end behave; 46 Copyright 2006 – Biz/ed
47. 47. Session 3 http://www.bized.co.ukData Objects 2-VariablesVariables are used for computations Represent only local information Declared inside a process can only be used inside a PROCESS (in sequential code).Variable declaration architecture behave of MPU is begin process(…) variable x, y : std_logic ; variable intbus : std_logic_vector(7 downto 0); begin . . . end process ; . . end behave; 47 Copyright 2006 – Biz/ed
48. 48. Session 3 http://www.bized.co.ukData Objects 2-VariablesAssignment Operator Assigned using “:=” Blocking AssignmentExample var_x :=“0000”; var_1 :=„1‟;Behavior its value can not be passed out directly its update is immediate, so the new value is used in the next line of code. As long as signal and variable have same type they can be assign to eachother . 48 Copyright 2006 – Biz/ed
49. 49. Session 3 http://www.bized.co.ukObjective -Be familiar with variable declaration -Using variable inside the process Example 17 49 Copyright 2006 – Biz/ed
50. 50. Session 3 http://www.bized.co.ukprocess(……) variable variable1: integer :=1; variable variable2: integer :=2; variable variable3: integer :=3;begin ……… variable1 := variable2; variable2 := variable1 + variable3; variable3 := variable2; RESULT <= variable1 + variable2 + variable3; ………..end process; 50 Copyright 2006 – Biz/ed
51. 51. Session 3 http://www.bized.co.ukObjective -Be familiar with variables declaration -Using Signals inside and outside the process Exercise 3 51 Copyright 2006 – Biz/ed
52. 52. Session 3 http://www.bized.co.uk -- Force A = "001"library IEEE;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;entity signal_lab is port( A : in std_logic_vector(2 downto 0) );End signal_lab;Architecture behave of signal_lab isbeginprocess (A)Variable Z,G,F,X : std_logic_vector(2 downto 0);Begin G := A + A; F := G + A; X := G + F; Z := X + F;end process ;end behave; 52 Copyright 2006 – Biz/ed
53. 53. Session 3 http://www.bized.co.ukData Objects Initializationmade when we declare the variable or the functionusing := signal sigbus : std_logic_vector(7 downto 0) := "01011110"; variable z : std_logic := 1; variable varbus : std_logic_vector(3 downto 0) := "0001"; 53 Copyright 2006 – Biz/ed
54. 54. Session 3 http://www.bized.co.uk 2-InitializationsSignals inside your design should have initial valuesSynthesis tools ignore initial values specified for a variable or a signal in its declaration.The best way for initialization is to initialize the signals when the reset is active. If reset = „1‟ then sig_1 <= „0‟ ; sig_2 <= “00000”; sig_3 <= “10101010”; out_1 <= “00” elsif ris…… ……… 54 Copyright 2006 – Biz/ed
55. 55. Session 3 http://www.bized.co.ukData Objects Signal vs Variable Signals VariablesDeclaration Internal : Inside Process Declaration Inside Architecture Declaration External : Inside Port entityAssignment Non-Blocking Assign <= Blocking Assign :=Initialization := :=Update After the process suspend ImmediatelyScope Seen by the whole code Local onside process Can be used in either type of code, Can only be used inside concurrent or sequential. a sequential codeUTILITY Represents circuit interconnects Represents local information (wires) 55 Copyright 2006 – Biz/ed
56. 56. Session 3 http://www.bized.co.ukData Objects Object Scope-Ports are signals and declared at the top level (entity)-Within the architecture, local signals are declared-Within the process, local variables can be declared 56 Copyright 2006 – Biz/ed
57. 57. Session 3 http://www.bized.co.ukData Objects 3-ConstantsA constant can have a single value of a given type and cannot be changed duringthe simulation.Constant Declaration constant <con_name> : <data_type>; := <con_value>;Constants can be declared at the start of an architecture and can then be usedanywhere within the architecture.Constants declared within a process can only be used inside that specific aProcess.Example CONSTANT set_bit : BIT := 1; 57 Copyright 2006 – Biz/ed
58. 58. Session 3 http://www.bized.co.ukObjective -General Example Example 18 58 Copyright 2006 – Biz/ed
59. 59. Session 3 http://www.bized.co.ukCalculate the values of var1, sig1& Qprocess (a,b) variable var1: integer;begin var1 := a + b; sig1 <= var1; Q <= sig1;end process; Var1 sig1 Q ExerciseA=1 3 4 6B=2 4A=2 During processB=3 Process suspendA=5 During processB=2 Process suspend 59 Copyright 2006 – Biz/ed
60. 60. Session 3 http://www.bized.co.ukCalculate the values of var1, sig1& Q Var1 sig1 Q A=1 3 4 6 B=2 A=2 5 4 6 During process B=3 5 5 4 Process suspend A=5 7 5 4 During process B=2 7 7 5 Process suspend process (a,b) variable var1: integer; begin var1 := a + b; sig1 <= var1; Q <= sig1; end process; 60 Copyright 2006 – Biz/ed
61. 61. Session 3 http://www.bized.co.uk• Do one of the Previous Exercises on ModelSim to sense the difference between signals and variables lab 4 61 Copyright 2006 – Biz/ed
62. 62. Session 3 http://www.bized.co.ukAssignment Session-3Study the three sessions well 62 Copyright 2006 – Biz/ed