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Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
Session seven
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Session seven
Session seven
Session seven
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Session seven

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  • 1. http://www.bized.co.uk Session 7Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
  • 2. http://www.bized.co.ukContents - Structural Description - Generic Statements - Packages 7 - Generate Statements -For Generate 2 Copyright 2006 – Biz/ed
  • 3. Session 7 http://www.bized.co.ukthe main objective here is to linkbetween many blocks to getgeneral block. Block_1 Structural description Block_3 Block_2 3 Copyright 2006 – Biz/ed
  • 4. Session 7 http://www.bized.co.ukStructural Description Structural description allows having multiple levels of hierarchy in the design Top- Down Design define general block that has general inputs and outputs after that we can write the collection of the mini blocks inside it. 4 Copyright 2006 – Biz/ed
  • 5. Session 7 http://www.bized.co.ukStructural Description 1) Component declaration component <component_name> port ( <port_names>: <mode> <type>; <port_names>: <mode> <type>; . . . ); end component; Note that the definition of the component is like the definitionof the entity Think as Hardware 5 Copyright 2006 – Biz/ed
  • 6. Session 7 http://www.bized.co.ukStructural Description 2) Component instantiation and Interconnections instance_name: component_name port map (signal1, signal2,…); each signal is written in the position that describe which port it belongs to which means that the first signal written here represent the first port in the component very important note: if you neednt use special output port you can write the key word open (that mean this port will be unconnected). Think as Hardware 6 Copyright 2006 – Biz/ed
  • 7. Session 7 http://www.bized.co.uk Example 28 7 Copyright 2006 – Biz/ed
  • 8. Session 7 http://www.bized.co.ukentity test is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : d : in in STD_LOGIC; STD_LOGIC; And f : out STD_LOGIC); gateend test;architecture Behavioral of test is Or gatecomponent or_gate is Port ( in1 : in STD_LOGIC; And in2 : in STD_LOGIC; gate out_or : out STD_LOGIC);end component ;component and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC);end component;signal sig1,sig2 : std_logic;beginu1:and_gate port map (a,b,sig1);u2:and_gate port map (c,d,sig2);u3:or_gate port map (sig1,sig2,f);end Behavioral; 8 Copyright 2006 – Biz/ed
  • 9. Session 7 http://www.bized.co.ukStructural Description2) Component instantiation and Interconnections <instance_name>: <component_name > port map( <port_name> => <sig_name>, <port_name> => <sig_name>, . . . <port_name> => <sig_name> );very important note:if you neednt use special output port you can write the key word open (thatmean this port will be unconnected). Think as Hardware 9 Copyright 2006 – Biz/ed
  • 10. Session 7 http://www.bized.co.uk Example 29 10 Copyright 2006 – Biz/ed
  • 11. Session 7 http://www.bized.co.ukEntity test is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; begin d : in STD_LOGIC; u1:and_gate f : out STD_LOGIC);end test; port map (in1 => a, in2 => b, out_and => sig1);Architecture Behavioral of test is u2:and_gatecomponent or_gate is port map (in1 => c, Port ( in1 : in STD_LOGIC; in2 => d, in2 : in STD_LOGIC; out_and => sig2); out_or : out STD_LOGIC);end component ; u3:or_gatecomponent and_gate is port map (in1 => sig1, Port ( in1 : in STD_LOGIC; in2 => sig2, in2 : in STD_LOGIC; out_or => f); out_and : out STD_LOGIC);end component;signal sig1,sig2 : std_logic; end Behavioral; 11 Copyright 2006 – Biz/ed
  • 12. Session 7 http://www.bized.co.uk lab 14 12 Copyright 2006 – Biz/ed
  • 13. Session 7 http://www.bized.co.ukEntity comp4 is port ( a , b : in std_logic_vector(3 downto 0); eq : out std_logic );End comp4 ;Architecture struct of comp4 isComponent xnor_2 is port ( g , f : in std_logic ; y : out std_logic );End component ;Component and_4 is port ( in1, in2, in3, in4 : in std_logic ; out : out std_logic );End component ;Signal x : std_logic_vector ( 3 downto 0 ) ;Begin U1 : xnor_2 port map ( a(0) , b(0) , x(0) ) ; U2 : xnor_2 port map ( a(1) , b(1) , x(1) ) ; U3 : xnor_2 port map ( a(2) , b(2) , x(2) ) ; U4 : xnor_2 port map ( a(3) , b(3) , x(3) ) ; U5 : and_4 port map ( x(0) , x(1) , x(2) , x(3) , eq ) ;End struct ; 13 Copyright 2006 – Biz/ed
  • 14. Session 7 http://www.bized.co.uk Generic Statement 14 Copyright 2006 – Biz/ed
  • 15. Session 7 http://www.bized.co.ukGeneric StatementVHDL provides an easy way to create generic design units that canbe used several times with different properties in the designhierarchy 4-bit counter N-bit counter 8-bit counter Hardware Think as 15 Copyright 2006 – Biz/ed
  • 16. Session 7 http://www.bized.co.ukGeneric declarationgeneric ( <identifier>: type [:= default_value]; <identifier>: type [:= default_value]) ); 16 Copyright 2006 – Biz/ed
  • 17. Session 7 http://www.bized.co.uk• Generic AND Gate Example 30 17 Copyright 2006 – Biz/ed
  • 18. Session 7 http://www.bized.co.uklibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;Entity generic_and is generic (N : integer := 4 ); port(A, B: in std_logic_vector (N-1 downto 0); Z : out std_logic_vector(N-1 downto 0) );End entity;Architecture behave of generic_and isBegin Z <= A and B;End architecture 18 Copyright 2006 – Biz/ed
  • 19. Session 7 http://www.bized.co.uk• N-Bit Full Adder Example 31 19 Copyright 2006 – Biz/ed
  • 20. Session 7 http://www.bized.co.uk C_in A N bit Sum Full Adder BEntity F_adder isGeneric ( N : integer := 4 ); C_outPort ( A, B : in std_logic_vector(N-1 downto 0) ; C_in : in std_logic ; Sum : out std_logic_vector(N-1 downto 0); C_out : out std_logic) ;End F_adder ; 20 Copyright 2006 – Biz/ed
  • 21. Session 7 http://www.bized.co.ukArchitecture struct of f_adder isComponent n_adder Generic ( N : integer := 4 ); Port ( A, B : in std_logic_vector(N-1 downto 0) ; C_in : in std_logic ; Sum : out std_logic_vector(N-1 downto 0); C_out : out std_logic) ; C_inEnd component ;Begin AU1 : n_adder generic map (8) port map ( A => acc , N bit Sum B => b_reg , Full Adder c_in => E , B sum => result , c_out => carry_out ) ;End struct C_out 21 Copyright 2006 – Biz/ed
  • 22. Session 7 http://www.bized.co.uk package 22 Copyright 2006 – Biz/ed
  • 23. Session 7 http://www.bized.co.ukInstead of declaring all components can declare all components in aPACKAGE, and INCLUDE the package once 1) This makes the top-level entity code cleaner 2) It also allows that complete package to be used by another designerA package can contain 1) Components 2) Functions, Procedures 3) Types, Constants 23 Copyright 2006 – Biz/ed
  • 24. Session 7 http://www.bized.co.uk• Logic circuit by using package Example 32 24 Copyright 2006 – Biz/ed
  • 25. Session 7 http://www.bized.co.uklibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; Andpackage logic_circuit is gatecomponent or_gate is Port ( in1 : in STD_LOGIC; Or gate in2 : in STD_LOGIC; out_or : out STD_LOGIC); Andend component ; gatecomponent and_gate is Port ( in1 : in STD_LOGIC; in2 : in STD_LOGIC; out_and : out STD_LOGIC);end component;constant const1: STD_LOGIC_vector (3 downto 0) := "0011"; ---const definitionend logic_circuit; 25 Copyright 2006 – Biz/ed
  • 26. Session 7 http://www.bized.co.uklibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use work.logic_circuit.all; -----definition of the packageentity test is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; out1: out STD_LOGIC_vector (3 downto 0); And f : out STD_LOGIC);end test; gatearchitecture Behavioral of test issignal sig1,sig2 : std_logic; Or gatebeginu1:and_gateport map ( in1 => a, And in2 => b, out_and => sig1); gateu2:and_gateport map ( in1 => c, in2 => d, out_and => sig2);u3:or_gateport map ( in1 => sig1, in2 => sig2, out_or => f);out1<= const1; ------- const usingend Behavioral; 26 Copyright 2006 – Biz/ed
  • 27. Session 7 http://www.bized.co.uk Generate statement 27 Copyright 2006 – Biz/ed
  • 28. Session 7 http://www.bized.co.uk• The generate statement simplifies description of regular design structures.Usually it is used to specify a group of identical components using just onecomponent specification and repeating it using the generate mechanism.For generate declaration : Label : for identifier IN range GENERATE (concurrent assignments) . . . END GENERATE; 28 Copyright 2006 – Biz/ed
  • 29. Session 7 http://www.bized.co.uk• SEREIS OF XOR GATES Example 33 29 Copyright 2006 – Biz/ed
  • 30. Session 7 http://www.bized.co.ukENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC );END parity; 30 Copyright 2006 – Biz/ed
  • 31. Session 7 http://www.bized.co.uk xor_out(1) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6)xor_out(1) <= parity_in(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);parity_out <= xor_out(6) XOR parity_in(7); 31 Copyright 2006 – Biz/ed
  • 32. Session 7 http://www.bized.co.ukxor_out(0) xor_out(1) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6) xor_out(7)xor_out(0) <= parity_in(0);xor_out(1) <= xor_out(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);xor_out(7) <= xor_out(6) XOR parity_in(7);parity_out <= xor_out(7); 32 Copyright 2006 – Biz/ed
  • 33. Session 7 http://www.bized.co.ukARCHITECTURE parity_dataflow OF parity ISSIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN 1 TO 7 GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE G2; parity_out <= xor_out(7);END parity_dataflow; 33 Copyright 2006 – Biz/ed
  • 34. Session 7 http://www.bized.co.uk• N- BIT REGISTER Example 34 34 Copyright 2006 – Biz/ed
  • 35. Session 7 http://www.bized.co.uk reset si so r r r r d q si q d q d q z0 clk z1 clk z2 clk z3 clk z4 clock 35 Copyright 2006 – Biz/ed
  • 36. http://www.bized.co.ukNext Session Evaluation Test Copyright 2006 – Biz/ed
  • 37. Session 7 http://www.bized.co.ukQuestions Session-7 37 Copyright 2006 – Biz/ed
  • 38. Session 7 http://www.bized.co.ukTake Your Notes Print the slides and take your notes here--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 38 Copyright 2006 – Biz/ed
  • 39. Session 7 http://www.bized.co.ukTake Your Notes Print the slides and take your notes here--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 39 Copyright 2006 – Biz/ed
  • 40. Session 7 http://www.bized.co.ukSee You Next Session 40 Copyright 2006 – Biz/ed

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