• Share
  • Email
  • Embed
  • Like
  • Save
  • Private Content
Session nine
 

Session nine

on

  • 387 views

 

Statistics

Views

Total Views
387
Views on SlideShare
387
Embed Views
0

Actions

Likes
0
Downloads
28
Comments
0

0 Embeds 0

No embeds

Accessibility

Categories

Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Session nine Session nine Presentation Transcript

    • http://www.bized.co.uk Session 9Prepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
    • http://www.bized.co.uk 9 -Sequential Statements -Loops For-WhileContents -Next-Exit Statements -Wait Statement -Null Statement -Assert Statement -Functions -Procedures -Test Benches -Dealing with Files -Modelsim and Do Files 2 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk Sequential Statements 3 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukLoop statementDeclaration label : loop Sequential statements contains the conditions to exit the loop end loop label ; Note that: In order to exit from a loop an exit statement has to be used. 4 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukClock using loopClock : process(clk) begin L1: loop clk <= not clk after 5 ns;End loop L1;End process; Example 39 5 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukCounter using Exit statementL2 : loop A := A+1; Example 40Exit L2 when A> 10;End loop l2; 6 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukWhile Loop statementDeclarationwhile <condition> loop Sequential statements;end loop ; 7 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.uk• Counter using while loopWhile count < 10 loop count <= count +1; ExampleEnd loop; 41 8 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukFOR Loop statementDeclarationfor <identifier> in range loop Sequential statements;end loop ; 9 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.uk• 8 bit shift register Example 42 10 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukFor i in 1 to 7 loop reg (i-1) <= reg(i); Shift RightEnd loop; 7 6 5 4 3 2 1 0Note : no need to define index “ i ” 11 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukNext statementA statement that may be used in a loop to cause the next iteration. [ label: ] next [ label2 ] [ when condition ] ;Example next; next outer_loop; next when A>B; next this_loop when C=D or done; -- done is a Boolean variable 12 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukExit statementA statement that may be used in a loop to immediately exit the loop. [ label: ] exit [ label2 ] [ when condition ] ;Example exit; exit outer_loop; exit when A>B; exit this_loop when C=D or done; -- done is a Boolean variable 13 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukNull statementUsed when a statement is needed but there is nothing to do. [ label: ] null ;Examplenothing : null; 14 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukReturn statementRequired statement in a function, optional in a procedure. [ label: ] return [ expression ] ; 15 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukWait statementThe wait statement is a statement that causes suspension of a process or a procedure.wait;wait on signal_list;wait until condition;wait for time;Important NotesThe wait statement can be located anywhere between begin and end process.A process with a sensitivity list may not contain any wait statements. 16 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukExamples on Wait StatementExample 43signal S1, S2 : Std_Logic;...process begin ... wait on S1, S2;end process;After executing all statements, the process will be suspended on the waitstatement and will be resumed when one of the S1 or S2 signals changes itsvalue. 17 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukExamples on Wait StatementExample 44wait until Enable = 1;-- this is equivalent to-- loop-- wait on Enable;-- exit when Enable = 1;-- end loop;In this example, the wait statement will resume the process when the Enablesignal changes its value to 1.This is equivalent to the loop described in the comment below the first line. Pleasenote that the process is resumed on any change of the Enable signal. However, itwill awake the rest of the process only when the new value is 1. 18 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukExamples on Wait StatementExample 45wait for 50 ns;A process containing this statement will be suspended for 50 ns.Example 46BIN_COMP : processbegin wait on A, B until CLK = 1; ...end process;The process BIN_COMP is resumed after a change on either A or B signal, butonly when the value of the signal CLK is equal to 1. 19 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukExamples on Wait StatementExample 47G: processbegin G0 <= 1 after 5 ns, 0 after 10 ns, 1 after 15 ns, 0 after 20 ns; G1 <= 1 after 5 ns, 0 after 15 ns; wait;end process G;In this process the values of signals G1 and G0 are set to 11, 10, 01, and 00at the time intervals 5, 10, 15 and 20 ns, respectively. When the wait statementis encountered, the process is suspended forever. 20 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukSubprograms : Functions and ProceduresFunctions and procedures in VHDL, which are collectively known as subprograms, aredirectly analogous to functions and procedures in a high-level software programminglanguage such as C or Pascal.A procedure is a subprogram that has an argument list consisting of inputs andoutputs, and no return value.A function is a subprogram that has only inputs in its argument list, and has a returnvalue. 21 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukFunctionsDeclarationfunction identifier [ ( formal parameter list ) ] return a_type isbegin sequential statements return some_value; -- of type a_type end function identifier ;Example function random return float is variable X : float; begin -- compute X return X; end function random ; 22 Copyright 2006 – Biz/ed
    • Session 8 http://www.bized.co.ukProceduresDeclaration procedure identifier [ ( formal parameter list ) ] is declaration begin sequential statements end procedure identifier ;Example procedure print_header is use STD.textio.all; variable my_line : line; begin write ( my_line, string("A B C")); writeline ( output, my_line ); end procedure print_header ; 23 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk Test-Bench 24 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukTest-Bench Testbenches are used to test the design in a programmatic way Testbench is used to: Compare output responses against expected values Test Bench Is my design functioning correctly? Signal generator UUT Osc. Think as Hardware 25 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukAND_GATE_TB Example 48 26 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukLIBRARY ieee;USE ieee.std_logic_1164.all;Entity and_tb is -- do we need ports here?End entity; Testbench--------------------------------------------architecture waveform of and_tb is Stimulus component AND_gate generators AND port (a : in std_logic; b : in std_logic; c : out std_logic); end component; signal x, y, z : std_logic;Begin x <= 0 , 1 after 40 ns; y <= 0 , 1 after 20 ns, 0 after 40 ns, 1 after 60 ns; uut : AND_gate PORT MAP ( a => x, b => y, c => z );End architecture; 27 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukAssertionThe ASSERT statement is a very useful statement for reporting textual stringsto the designer. The ASSERT statement checks the value of a booleanexpression for true or false. If the value is true, the statement does nothing. Ifthe value is false, the ASSERT statement outputs a userspecified text string tothe standard output to the terminal.Assert statementCheck a Boolean conditionReport statementDefine a message that will be displayed when an error is foundSeverity statementInform simulator how severe the situation is – form just a general noteto system failure Think as Hardware 28 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukAssertion Think as Hardware 29 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukAssertion Think as Hardware 30 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk• Counter Testbench Example 49 31 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uklibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;--------------------------------------------entity test isport (clk, reset : in std_logic; count : out std_logic_vector(3 downto 0)); end test;--------------------------------------------architecture Behavioral of test is signal count_sig : std_logic_vector(3 downto 0) ;begin count <= count_sig; --------------------- process(clk,reset) begin if(reset=1) then count_sig <=(others => 0); elsif(clkevent and clk=1) then count_sig <= count_sig +1; end if; end process; ---------------------- end Behavioral; 32 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukLIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;----------------------------------------------------------------------------- entity declaration for your testbench.-- Dont declare any ports hereENTITY test_tb ISEND test_tb;---------------------------------------------------------------------------ARCHITECTURE behavior OF test_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT test --test is the name of the module needed to be tested. --just copy and paste the input and output ports of your module as such. PORT( clk : IN std_logic; count : OUT std_logic_vector(3 downto 0); reset : IN std_logic ); END COMPONENT;-------------------------------------------- 33 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk -------------------------------------------- --declare inputs and initialize them signal clk : std_logic := 0; signal reset : std_logic := 0;-------------------------------------------- --declare outputs and initialize them signal count : std_logic_vector(3 downto 0);-------------------------------------------- -- Clock period definitions constant clk_period : time := 1 ns;--------------------------------------------BEGIN -- Instantiate the Unit Under Test (UUT) uut: test PORT MAP ( clk => clk, count => count, reset => reset ); 34 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk-- Clock process definitions-- clock with 50% duty cycle is generated here. clk_process :process begin clk <= 0; wait for clk_period/2; --for 0.5 ns signal is 0. clk <= 1; wait for clk_period/2; --for next 0.5 ns signal is 1. end process;---------------------------------------------- Stimulus process stim_proc: process begin wait for 7 ns; reset <=1; wait for 3 ns; reset <=0; wait for 17 ns; reset <= 1; wait for 1 ns; reset <= 0; wait; end process;END; 35 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk• Reading from files Example 50 36 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukLIBRARY ieee;USE ieee.std_logic_1164.ALL;use STD.textio.all; --Dont forget to include this library for file operations.ENTITY read_file ISEND read_file;ARCHITECTURE tb OF read_file IS signal bin_value : std_logic_vector(3 downto 0):="0000";BEGIN--Read processprocess file file_pointer : text; variable line_num : line; variable line_content : string(1 to 4); variable char : character:=0;begin 37 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukfile_open(file_pointer,"C:read.txt",READ_MODE);--Open the file read.txt from the specified location for reading(READ_MODE).while not endfile(file_pointer) loop --till the end of file is reached continue.readline (file_pointer,line_num); --Read the whole line from the fileREAD (line_num,line_content); --Read contents of the line from file into variable.--For each character in the line convert it to binary value to store in bin_value for j in 1 to 4 loop char := line_content(j); if(char = 0) then bin_value(4-j) <= 0; else bin_value(4-j) <= 1; end if; end loop;wait for 10 ns; --after reading each line wait for 10ns.end loop;file_close(file_pointer); --after reading all the lines close the file.wait;end process;end tb; 38 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk• Writing in files Example 51 39 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukLIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;use STD.textio.all;ENTITY write_file ISEND write_file;ARCHITECTURE beha OF write_file ISBEGIN --Write process process file file_pointer : text; variable line_content : string(1 to 4); variable bin_value : std_logic_vector(3 downto 0); variable line_num : line; variable i,j : integer := 0; variable char : character:=0; begin 40 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk --Open the file write.txt from the specified location for writing(WRITE_MODE). file_open(file_pointer,"C:write.txt",WRITE_MODE); --We want to store binary values from 0000 to 1111 in the file. for i in 0 to 15 loop bin_value := conv_std_logic_vector(i,4); --convert each bit value to character for writing to file. for j in 0 to 3 loop if(bin_value(j) = 0) then line_content(4-j) := 0; else line_content(4-j) := 1; end if; end loop; write(line_num,line_content); --write the line. writeline (file_pointer,line_num); --write the contents into the file. wait for 10 ns; --wait for 10ns after writing the current line. end loop; file_close(file_pointer); --Close the file after writing. wait; end process;end beha; 41 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk• Do files using in Modelsim Example 52 42 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.uk1) Create a library for working invlib work2) Compile your codevcom -93 -explicit -work work filename.vhd #3) Load it for simulationvsim entityname4) Open some selected windows for viewing view structure view signalsview wave #5) Show some of the signals in the wave windowadd wave -noupdate -divider Inputsadd wave –noupdate –color gold aadd wave -noupdate –color gold badd wave -noupdate -divider Outputsadd wave -noupdate –color yellow c6) Set some test patterns # a = 0, b = 0 at 0 nsforce a 0 0force b 0 0run 200 fs# a = 1, b = 0 at 10 nsforce a 1 10run 200 fs# a = 0, b = 1 at 20 nsforce a 0 20force b 1 20run 200 fs# a = 1, b = 1 at 30 ns 43 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukQuestions Session-9 44 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukTake Your Notes Print the slides and take your notes here--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 45 Copyright 2006 – Biz/ed
    • Session 9 http://www.bized.co.ukSee You Next Session 46 Copyright 2006 – Biz/ed