Evaluation test
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Evaluation test Presentation Transcript

  • 1. http://www.bized.co.uk Evaluation TestPrepared by Alaa Salah Shehata Mahmoud A. M. Abd El Latif Mohamed Mohamed Tala’t Mohamed Salah Mahmoud Version 02 – October 2011 Copyright 2006 – Biz/ed
  • 2. http://www.bized.co.uk Evaluation TestAnswer all questions in the following paperQuestions : 50 QuestionTime : 30 minuteFull Mark : 50 degree Copyright 2006 – Biz/ed
  • 3. Evaluation Test http://www.bized.co.ukQuestion Choice1 A2 B3 ---45678 Answer all questions in the paper91011121314151617181920 Copyright 2006 – Biz/ed
  • 4. 01 http://www.bized.co.ukA ________ is basically one bit of memory which is updated Evaluationwhen clock signal is high: Test A D-Flip Flop B D-Latch C T-Flip Flop D Register Evaluation Test Copyright 2006 – Biz/ed
  • 5. 02 http://www.bized.co.ukTrue or False : VHDL isEvaluation typed hardware description stronglylanguage Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 6. 03 http://www.bized.co.uk EvaluationGate Level Simulation isTest done before _____________ A Synthesis B Functional Simulation C Place and route D Configuration Evaluation Test Copyright 2006 – Biz/ed
  • 7. 04 http://www.bized.co.ukIn the code shown below, the rst signal is modeled as__________ EvaluationProcess(clk,rst) TestBegin if rst =‟0‟ then Q<=„0‟; elsif rising_edge(clk) then Q<= D; end if;End process; A Synchronous, Active High B Synchronous Active Low C Asynchronous Active High D Asynchronous Active Low Evaluation Test Copyright 2006 – Biz/ed
  • 8. 05 http://www.bized.co.uk EvaluationIF/CASE should be inside the body of________ Test A Entity B Architecture C Process D Package Evaluation Test Copyright 2006 – Biz/ed
  • 9. 06 http://www.bized.co.uk EvaluationHow many architectures can be associated with an entity? Test A One or more B Should be more than one C Only one D none Evaluation Test Copyright 2006 – Biz/ed
  • 10. 07 http://www.bized.co.ukTrue or False : any VHDL description must contain at least one Evaluationentity Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 11. 08 http://www.bized.co.uk Evaluation______cannot be declared inside process unit Test A variables B signals C Constants Evaluation Test Copyright 2006 – Biz/ed
  • 12. 09 http://www.bized.co.ukTrue or False : VHDL isEvaluation considered a High Level programminglanguage Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 13. 10 http://www.bized.co.ukTrue or False : Each statement in the architecture body Evaluationexecuted concurrently.Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 14. 11 http://www.bized.co.ukTrue or False : Each statement is in the process body Evaluationexecuted concurrently.Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 15. 12 http://www.bized.co.ukTrue or False : No difference meaning between variable Evaluationassignment and signal assignment. Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 16. 13 http://www.bized.co.ukTrue or False : An internal signal is declared before the Evaluationarchitecture begin. Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 17. 14 http://www.bized.co.uk EvaluationWhich of these is an valid identifier Test A _c1 B c_10 C Process D 1d Evaluation Test Copyright 2006 – Biz/ed
  • 18. 15 http://www.bized.co.uk process (CLK, CLEAR) begin if (CLEAR = 1) then Evaluation Q <= 0; Test elsif (CLKevent and CLK = 1) then Q <= D; end if; end process;The above code is the process for which flip flop?A T_FF B D_FFC latchD None of the above Evaluation Test Copyright 2006 – Biz/ed
  • 19. 16 http://www.bized.co.ukA VHDL statement used to create repetitive portions of Evaluationhardware is a(n) ____ Test A process B generate C instantiation D architecture Evaluation Test Copyright 2006 – Biz/ed
  • 20. 17 http://www.bized.co.uk EvaluationA full adder adds ____ Test A 2 single bits and one carry bit B 2 2-bit binary numbers C 2 4-bit binary numbers D None of the above Evaluation Test Copyright 2006 – Biz/ed
  • 21. 18 http://www.bized.co.ukTrue or False : The output of a Mealy machine can change Evaluationany time, regardless of the clock pulse. Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 22. 19 http://www.bized.co.ukWhich statement / clause in VHDL can be used to cover Evaluationunused states in a state Test machine? A unused B others C else D Dont_care Evaluation Test Copyright 2006 – Biz/ed
  • 23. 20 http://www.bized.co.ukHow many flip flops are necessary to design a state machine Evaluationwith 25 states? Test A 2 B 25 C 5 D 225 Evaluation Test Copyright 2006 – Biz/ed
  • 24. 21 http://www.bized.co.ukA finite state machine has an output determined only by the Evaluationpresent state of the system is ____. Test A Moore machine B Mealy machine C Max machine D Min machine Evaluation Test Copyright 2006 – Biz/ed
  • 25. 22 http://www.bized.co.ukTrue or False : The Component Instantiation are concurrent Evaluationstatements Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 26. 23 http://www.bized.co.uk EvaluationTrue or False : VHDL is case Sensitive Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 27. 24 http://www.bized.co.uk Evaluation„„<=‟‟ is______________ Test A Blocking assignment B Non-Blocking assignment Evaluation Test Copyright 2006 – Biz/ed
  • 28. 25 http://www.bized.co.ukWe use Internal Signals for: (choose all the apply) Evaluation Test A Internal connections in structural description B Intermediate calculations C Avoid illegal port usage situations Evaluation Test Copyright 2006 – Biz/ed
  • 29. 26 http://www.bized.co.ukStd_logic _vector and Std_logic are performed over Evaluationbit_vector and bit because … Test A They are “built – in” to language B They are longer names C They are case sensitive D They can represent values other than just 0 and 1 such as weak pull – up /down and high impedance Evaluation Test Copyright 2006 – Biz/ed
  • 30. 27 http://www.bized.co.ukTrue or False : Once the VHDL code has been written, it can be used either to Evaluationimplement the circuit inTest programmable device or can be submitted to a afoundry for fabrication of an ASIC chip A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 31. 28 http://www.bized.co.ukprocess (A, B) process begin begin C <= A and B;Evaluation Test C <= A and B; C <= 1; Wait on A, B;end process; C <= 1; Wait on A, B; end process; A Equivalent B Not-Equivalent Evaluation Test Copyright 2006 – Biz/ed
  • 32. 29 http://www.bized.co.uk EvaluationTrue or False : Sequential statements should be written inside a “process” Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 33. 30 http://www.bized.co.uk EvaluationVariables are updated_________ Test A Immediately B After the process suspends Evaluation Test Copyright 2006 – Biz/ed
  • 34. 31 http://www.bized.co.uk EvaluationSignals are updated_________ Test A Immediately B After the process suspends Evaluation Test Copyright 2006 – Biz/ed
  • 35. 32 http://www.bized.co.uk Evaluationres <= (a and not(b)) or Test (not(a) and b); this statement is : A True B Wrong Evaluation Test Copyright 2006 – Biz/ed
  • 36. 33 http://www.bized.co.uk EvaluationVHDL is __________ Test A Strongly typed language B Weakly typed language Evaluation Test Copyright 2006 – Biz/ed
  • 37. 34 http://www.bized.co.uk EvaluationIf data stored in the RAM location pointed by addr ,then add must be : Test A Integer B Std_logic_vector C Bit_vector Evaluation Test Copyright 2006 – Biz/ed
  • 38. 35 http://www.bized.co.ukIn the previous example ,the first waveform express (clk) and the second Evaluationexpress (input) TestThe last two waves express respectively : A Moore and Mealy B Mealy and Moore Evaluation Test Copyright 2006 – Biz/ed
  • 39. 36 http://www.bized.co.ukTo avoid cascaded look – up tables , what types of statements are preferred Evaluationfor Xilinx FPGA s ? Test A CASE B IF/ELSE Evaluation Test Copyright 2006 – Biz/ed
  • 40. 37 http://www.bized.co.uk EvaluationTrue or False : Place and Route is performed before Mapping Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 41. 38 http://www.bized.co.uk component add is port ( a : in Evaluation std_logic_vector(7 downto 0); b Test : in std_logic_vector(7 downto 0); dout : out std_logic_vector(7 downto 0)); end component add;begin cmp_add: add port map (open, b_in, open); A Legal B illegal; Evaluation Test Copyright 2006 – Biz/ed
  • 42. 39 http://www.bized.co.ukTrue or False : All VHDl codes that can be simulated are Evaluationsynthesizable Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 43. 40 http://www.bized.co.uk EvaluationTrue or False : The best Group is _____ Test A Start Group B Start Group C Start Group D Start Group Evaluation Test Copyright 2006 – Biz/ed
  • 44. 41 http://www.bized.co.ukSIGNAL a : std_logic;SIGNAL b : std_logic;Signal C : std_logic_vector(1 downto 0);….. Evaluation….. TestBeginB <= c(a); A Legal B Illegal C C should be output port to be write Evaluation Test Copyright 2006 – Biz/ed
  • 45. 42 http://www.bized.co.ukPROCESS (X) variable a: integer;type int is range -10 to 10; Evaluation variable d: int; TestBEGINd := a;END PROCESS; A Legal B Illegal Evaluation Test Copyright 2006 – Biz/ed
  • 46. 43 http://www.bized.co.uk EvaluationTrue or False : Record is a Group elements of different types Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 47. 44 http://www.bized.co.ukARCHITECTURE examp OF attrs IS Type states is (red, yellow, green); Evaluation signal state: states;Begin TestOutput <= state‟highEnd examp;Then the value of output equal A red B yellow C green Evaluation Test Copyright 2006 – Biz/ed
  • 48. 45 http://www.bized.co.ukTrue or False : EvaluationSignal data_bus : std_logic_vector(15 downto 0); Testdata_bus <= (1 | 4 | 7 => 1, 2 | 3 => 0, others => Z);Then the value of data_bus will equal“ZZZZZZZZ1ZZ100Z1” A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 49. 46 http://www.bized.co.ukARCHITECTURE examp OF attrs IS signal state: std_logic_vector(7 downto 0);Begin EvaluationProcess(clr,clk) Test Process(clr,clk)begin beginIf reset = „1‟ then If reset = „1‟ thenState<= “10000000”; State<= “10000000”;Elsif rising_edge(clk) then Elsif rising_edge(clk) thenState <= „0‟ & state; State <= state(0) & state;End if ; End if ;End process; End process;The above 2 processes are equal______ A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 50. 47 http://www.bized.co.uk EvaluationTrue or False : FPGA is faster than ASIC Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 51. 48 http://www.bized.co.uk EvaluationTrue or False : ASIC could be programmable more than time Test A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 52. 49 http://www.bized.co.ukSignal a,b,c: std_logic := „0‟;BeginProcess(a) EvaluationBegin Test a <= „1‟; b <= a; c <= b;End;After the Process suspend , the value of b = _______ A 1 B 0 Evaluation Test Copyright 2006 – Biz/ed
  • 53. 50 http://www.bized.co.ukTrue or False : Signal count: std_logic_vector(0 to 7Process(clr,clk) Evaluation ) TestVariable count: std_logic_vector(0 to 7); Beginbegin Process(clr,clk)If reset = „1‟ then beginCount <= “00000000”; If reset = „1‟ thenElsif rising_edge(clk) then Count <= “00000001”;Count <= count +1; Elsif rising_edge(clk) thenEnd if ; Count <= count +1;End process; End if ; End process;After 10 clock cycle the value of count in the last twoprocess will be equal (the same value) A True B False Evaluation Test Copyright 2006 – Biz/ed
  • 54. Evaluation Test http://www.bized.co.uk Copyright 2006 – Biz/ed