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# Digitalfundamentals chap7

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• 同是 D 功能，但触发方式不同，结果很不同 so 触发方式是重要的。
• The inputs A 1 , A 2 , and B are trigger inputs. The R INT terminal connects to a internal timing resistor. The C EXT and R EXT /C EXT terminals connect external timing capacitor and resistor.
• ### Digitalfundamentals chap7

2. 2. • Logic circuits – Combinational Circuits – Sequential Circuits Basic Block Flip-FlopsFloyd, Digital Fundamentals, 10th ed 2 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
3. 3. Flip-Flop 能够 存储 1 位二值 信号的基本单 元电 路发 器的功能：形象地说 ， 它具有“一触即发 ”的功能。 触 在输 入信号的作用下，输 出能够 从一种 状态 ( 0 或 1 ) 转变 成另 一种 状态 ( 1 或 0 ) 。 触发 器的特点：有记忆 功能的逻辑 部件。输 出状态 不 只与当前的输 入有关 ，还 与原来的输 出状态 有关 。 触发 器的分类 ： Bistable Monostable 按其稳态 工作状态 分：双稳态 触发 器、单稳态 触 发 器、无稳态 触发 器（多谐 振荡 器）； AstableFloyd, Digital Fundamentals, 10th ed 3 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
4. 4. CHAPTER OVERVIEW  Bistable devices have two stable states, called SET and RESET. They are used as storage devices.  Monostable devices (monostable trigger, one-shot) have one stable state. They are used as timers.  Astable devices (multivibrator) do not have stable state. They are used as waveform generators.Floyd, Digital Fundamentals, 10th ed 4 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
5. 5. 8-1 LATCHES( 锁存器 ) • A latch is a type of bistable logic device. 一种双稳态临时存储设备，和触发器类 似，只是改变状态的方式有所不同。 • There are two types of latches: – S-R latch ( SET-RESET latch) – D latch (Delay latch)Floyd, Digital Fundamentals, 10th ed 5 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
6. 6. The S-R Latch  An active-HIGH input S-R latch is formed with two cross- coupled NOR gates.  An active-LOW input S-R latch is formed with two cross- coupled NAND gates.Floyd, Digital Fundamentals, 10th ed 6 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
8. 8. 基本 S-R 锁存器 稳态 情况下，两输 出互补 交叉反馈 Q Q 两 个输 出端 两 个输 入端 R S 正是由于引入反馈 ，才使电 路具有记忆 功能 ! Active-LOW inputFloyd, Digital Fundamentals, 10th ed 8 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
9. 9. 输 入 R=0, S=1 时 置“ 0” Reset 若原状态 ： Q = 0 Q =1 ！： Q = 1 Q = 0 若原状态 Q 1 0 Q Q 0 1 Q 1 0 1 0 0R 0 1 S1 0R 1 1 S1 输 出仍保持 输 出变为 ： ： Q=0 Q=1 Q=0 Q=1Floyd, Digital Fundamentals, 10th ed 9 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
10. 10. 输 入 R=1, S=0 时 置“ 1” Set 若原状态 ： Q = 0 Q = 1 ！ 若原状态 ： Q = 1 Q = 0 Q 1 0 Q Q 0 1 Q 0 1 0 1 1R 1 0 S0 1R 1 0 S 0 输 出变为 ： 输 出保持： Q=1 Q=0 Q=1 Q= 0Floyd, Digital Fundamentals, 10th ed 10 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
11. 11. 输 入 R=1, S=1 时 保持！ 若原状态 ： = 1 Q = 0 Q 若原状态 ： Q = 0 Q = 1 Q 0 1 Q Q 1 0 Q 0 1 1 0 1R 1 0 S1 1R 0 1 S 1 输 出保持原状态 输 出保持原状态 ： ： Q=1 Q=0 Q=0 Q=1Floyd, Digital Fundamentals, 10th ed 11 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
12. 12. 输 入 R=0, S=0 时 Q 1 1 Q R 0 0 S Q 1 0R S 0 Q 1 输 出：全是 1 注意：当 RD 、 SD 同时 由 0 变 为 1 时 ，翻转 快的门输 出变 为 0 ，另 一个不得翻转 。因此 ，该 状态为 不定状态 。 不定Floyd, Digital Fundamentals, 10th ed 12 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
13. 13. 基本 S-R 锁 存器的功能表 ( 特性 表) R S Qn Qn+1 置位端 1 1 Qn Qn 保持原态S S Q 0 1 Qn 0 R R Q 1 0 Qn 1 复 位端 0 0 0 1* 次态 不定 逻辑 符号 0 0 1 1* Qn+1 S R 特性方程 Qn 0 0 1 1 n+ 1 Q = S + RQ n 0 0 1 11 1 0 00 * S + R = 1 约 束条件 · 0 1 1 1 1 0 *Floyd, Digital Fundamentals, 10 ed th 13 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
14. 14. Q Q R S Qn Qn+1 置位端 0 0 Qn Qn S S Q 0 1 Qn 1 R R Q 1 0 Qn 0 复 位端 1 1 0 0* 1 1 1 0* R 逻辑 符号S Active-HIGH input 特性方程 Qn+1 S R n+ 1 Qn 0 0 1 1 Q = S + RQ n 0 0 0 1 0 1 × 0 0 1 S⋅R= 0 约 束条件 * × 1 1 0 0 1 *Floyd, Digital Fundamentals, 10th ed 14 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
19. 19. S =1 R=0 Q Q S=0 0 S =× 1 R=0 R=× S=0 R=1 状态转换图 R 1 S 1 门 控 S-R 锁 存器特性表 同基本 S-R 锁 存器 EN R S Qn+1 输 出保持原 0 × × 态 Qn R S 1 0 0 Qn EN 1 0 1 1 10 Q n+ 1 = S + RQ n 1 1 0 0 SR = 0 约 束条件 1 1 1 1*Floyd, Digital Fundamentals, 10th ed 19 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
20. 20. 例：画出门控 S-R 锁存器的输出波形 。假设 Q 的初始状态 为 0。 Set Keep Reset Keep 使输 出全为 1 EN 保持原态 R 0 10 0 1 EN 撤去后 S 1 00 状态 不定 0 1 Q 1 0 保持 1 QFloyd, Digital Fundamentals, 10th ed 20 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
21. 21. The Gated D Latch 门 控 D 锁 存器特性表 Q Q D EN Qn+1 × 0 Qn 1 1 1 0 1 0 D Q EN D EN Q Q n+ 1 = D + RQ n S DQ n 逻辑 符号 SR = 0 约 束条件Floyd, Digital Fundamentals, 10th ed 21 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
24. 24. Latch vs. Flip-Flop • Bistable devices • Latch: change output at any time • Flip-Flop: – Synchronous – CLK – TriggerFloyd, Digital Fundamentals, 10th ed 24 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
25. 25. 8-2 EDGE-TRIGGERED FLIP-FLOPS • Edge-triggered flip-flops are synchronous bistable devices. Their outputs change states only at a specified point on a signal called clock (CLK).Floyd, Digital Fundamentals, 10th ed 25 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
30. 30. A method of Edge-Triggering S Q CLK Q R CLK 如果在脉冲的下跳沿触发 ，如何实现 ？Floyd, Digital Fundamentals, 10th ed 30 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
32. 32. Timing diagram CP D Q Truth Table CP D Q Q ↑ D D DFloyd, Digital Fundamentals, 10th ed 32 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
34. 34. Edge-Triggered J-K FF S J Q CLK Q K R S = JQ n Q n + 1 = S + RQ n SR = = JQ +约K + Q )Q n n n R = KQ n 0 ( 束条件 = JQ + KQ n nFloyd, Digital Fundamentals, 10th ed 34 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
35. 35. ①IF J=1,K=0,Q0=0;THEN G1 enabled, Q=1 (SET)②IF J=0,K=1,Q0=1;THEN G2 enabled, Q=0 (RESET)③IF J=0,K=0; THEN no change④IF J=1,K=1; THEN change to oppositestate(Toggle)Floyd, Digital Fundamentals, 10th ed 35 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
36. 36. J =1 K=× J K CLK Qn+1 J=0 J0 Q 1 J =× K=× K=0 0 0 × Qn C J =× K K = 1Q 0 1 ↑ ↓ 0 JK 触发 器的状态 转换图 1 0 ↑ ↓ 1 Q n+1 = JQ + KQ n n n 1 1 ↓ ↑ Q CP J 1 0 0 1 K 0 1 0 1 QFloyd, Digital Fundamentals, 10th ed 36 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
39. 39. Asynchronous Preset and Clear Inputs Before operation, a flip-flop must have a known state. This is done by preset ( direct set) and clear (direct reset) inputs. These are inputs that affect the state of the flip-flop independent of the clock.Floyd, Digital Fundamentals, 10th ed 39 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
40. 40. J-K Flip-Flop with Preset and Clear Inputs PRE 0 J 1Q CLK 1 0 K 0 1 Q CLR 1 J S Q C 当异步 置位或复 位输 入端出现 有效 K R Q 电压 信号，则 不管 J 、 K 端输 入如 何，触发 器被立即置位（ 1 ）或复Floyd, Digital Fundamentals, 10th ed 40 © 2009） Education, Upper Saddle River, NJ 07458. All Rights Reserved 位（ 0 Pearson
45. 45. Comparison of edge-triggered and level-triggered E/CP D Q(LEVEL) Q(EDGE)Floyd, Digital Fundamentals, 10th ed 45 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
46. 46. “ 空翻”现象 EN Q Q Qn=0 =1 Q 0 1 =0 Qn+1=1 脉冲宽 度不合适 时 ，可能会产 生 RD SD “空翻”现 象。 0 1 1 0 归纳 ： 在 EN ＝ 1 1 0 1 期EN 间 ，次态 Qn+1 必 0 R S 然是对 原态 Qn 的否 EN Q 定 !Floyd, Digital Fundamentals, 10th ed 46 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
47. 47. 1 Q n + 1 = JQ n + KQ n J S Q = 1 ×Q + 0 ×Q n n C K R Q =Q n 1 脉冲宽 度的变 化， Q 不会导 致“空翻” Q 。Floyd, Digital Fundamentals, 10th ed 47 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
48. 48. 8-3 MASTER-SLAVE FLIP-FLOPS Master-slave flip-flops are pulse- triggered. A master-slave flip-fop consists of two gated latches. Data are entered into it at the leading edge of the clock, but the output does not reflect the input state until the trailing edge. Master-slave flip-flops have largely been replaced by the 48 edge-triggered devices.Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
51. 51. JK 触发 器的工作原理 ： Q Q 保持原态 J=K=0 时 ： Q Q F从 R2 C S2 主触发 器被 封锁 ，保持 CP 原态 F主 R1 C S1 =0 K CP J =0Floyd, Digital Fundamentals, 10th ed 51 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
52. 52. J=K=1 时 ： 1 Q Q Qn=1 时 0 Qn+1=0 Q Q F从 R2 C S2 1 CP 0 F主 R1 C S1 1 0 =1 K CP J =1Floyd, Digital Fundamentals, 10th ed 52 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
53. 53. J=K=1 时 ： 0 Q Q Qn=0 时 1 Qn+1=1 Q Q F从 每 来一个脉 R2 C S2 冲输 出翻转 一次，具有 0 CP 1 计 数功能。 F主 R1 C S1 0 1 =1 K CP J =1Floyd, Digital Fundamentals, 10th ed 53 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
54. 54. J=1 ， K=0 时 Q Q Qn=0 时 1 ： Qn+1=1 Q Q F从 R2 C S2 CP 1 F主 R1 C S1 0 1 =0 K CP J =1Floyd, Digital Fundamentals, 10th ed 54 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
55. 55. Q Q Qn=1 时 J=1 ， K=0 时 ： Qn+1 =1 Q Q F从 F 主被封， R2 S2 C 保持原态 CP F主 0 R1 C S1 0 1 0 =0 K CP J =1Floyd, Digital Fundamentals, 10th ed 55 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
56. 56. J=0 ， K=1 时 ： Q Q Qn+1=0 Q Q F从 R2 C S2 同样 原理： CP F主 R1 C S1 =1 K CP J =0Floyd, Digital Fundamentals, 10th ed 56 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
58. 58. 8-4 Flip-Flops Operation Characteristics • Propagation delay times • Set-up time • Hold Time • Maxim Clock Frequency • Pulse Widths • Power DissipationFloyd, Digital Fundamentals, 10th ed 58 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
63. 63. Other parameters • Maxim Clock Frequency • Pulse Widths • Power DissipationFloyd, Digital Fundamentals, 10th ed 63 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
65. 65. 8-5 FLIP-FLOP APPLICATIONS • Flip-flops are building blocks for sequential logic. There are many applications of flip- flops. For example, by using n flip-flops, we can achieve – An n-bit parallel data storage – A frequency divider of 2n – A modulo 2n counterFloyd, Digital Fundamentals, 10th ed 65 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
66. 66. 4-bit Register Used for Data Storage • The data on the D inputs are stored simultaneously by the flip-flops on the positive edge of the clock.Floyd, Digital Fundamentals, 10th ed 66 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
67. 67. Divide-by-2 Device • When a pulse waveform is applied to the clock input, the Q output is a square wave with one-half the frequency of the clock input.Floyd, Digital Fundamentals, 10th ed 67 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
68. 68. Divide-by-4 Device • When a pulse waveform is applied to the clock input, the Q output is a square wave with one-half the frequency of the clock input.Floyd, Digital Fundamentals, 10th ed 68 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
69. 69. Modulo 4 Counter • If we take QA as the LSB and QB as the MSB, a 2-bit sequence is produced as the flip-flops are clocked.Floyd, Digital Fundamentals, 10th ed 69 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
70. 70. Q0 Q1 1 J0 1 J1 CLK Qn+1=JQn+KQn=Qn K0 K1 CLK f Q0 0 1 0 1 0 1 0 1 0 二分频 Q1 0 1 1 0 0 1 1 0 0 四分频 Q1 Q0 n 个触发 器可以实现 2n10 00 11 分频 01 Modulo 4 Counter 2n 2 位二进 制减 法计 数器 nFloyd, Digital Fundamentals, 10th ed 70 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
71. 71. Schmitt-Trigger • 普通门电路的电压传输特性曲线 工作区： AB 段（截止区） UI<0.6V UO=UOH DE 段（饱和区） UI>1.5V UO=UOL 线性区： BC 段 0.6V<UI<1.3V UI UO 转折区： CD 段 1.3V<UI<1.5V UI Upper Saddle River, NJ 07458. All Rights Reserved UOFloyd, Digital Fundamentals, 10 ed th 71 © 2009 Pearson Education,
72. 72. 1. 施密特触发 器 Schmitt-Trigger a special type of bi-stable device that has two 特点： threshold voltages (1) 输 入信号上升和下降过 程中电 路状态转换对应 的的触 发电 平不同； (2) 输 出信号的边 沿很陡 。 应 用：波形变换 、脉冲整形、脉冲鉴 幅、构 成多谐 振荡 器 (1) 可将边 沿变 化缓 慢的波形整形为边 沿陡 峭的波形； (2) 可将加在矩形脉冲高、低电 平上的噪声有效地消除。 R2 两级 CMOS 反相器构 成的施密特触发 器： R1 vo1 vI vo v′ I G1 G2 ′ voFloyd, Digital Fundamentals, 10th ed 72 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
73. 73. 回顾 ： MOS 管 CMOS logic uses the MOSFET in complementary pairs as its basic element. A complementary pair uses both p-channel and n-channel enhancement MOSFETsFloyd, Digital Fundamentals, 10th ed 73 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
75. 75. R2 R2 VT+ R1 vo1 v ′ = VTH I ≈ VT + vo 0 R1 + R2 vI v′ I G1 G2 VTH ′ vo G1 、 G2 的 VTH ≈1/2VDD R1<R2 vo1 当 vI= 0 时 vO= vOL≈0, vI ≈ 0 vI 当 vI 从 0 逐渐 升高并达 到 vI = VTH 时 ， threshold折区 Positive-going G1 进 入转 voltage vO1 vO 正向阈值电压 ： v′ I R1 + R2  R1  VT + = VTH =  1 +  VTH R2  R2  正反馈 使得电 路状态 迅速翻转为 vO= vOH ≈ VDDFloyd, Digital Fundamentals, 10th ed 75 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
76. 76. R2 R1 vo1 VDD VT- vo vI v′ VTH G1 G2 I ′ vo 当 vI 从高电 平逐渐 下降并达 到 vI = VTH 时 ， vI 的下降引 发 又一个正反馈过 程 v′ vO1 vO I 电 路状态 迅速翻转为 vO= vOL ≈ 0 R1 v ′I = VTH ≈ VT − + (VDD − VT − ) Negative-going threshold voltage R1 + R2 2VTH R1 + R2 R1  R1  负 向阈值电压 ： VT − = VTH − VDD =  1 −  VTH R2 R2 R2 All © 2009 Pearson Education, Upper Saddle River, NJ 07458.  Rights Reserved Floyd, Digital Fundamentals, 10 ed th 76
77. 77. vO R1 R2 → 2 VTH ← R2 R1 vo1 vI vo v′ I G1 G2 ′ vo ′ R1 O VT + VDD vI vO → 2 VTH ← VT − VTH R2 输 入输 出同相 回差电压 R1 v I ∆ VT = VvO − VT − I= 2 R VTHO′ O T+ v v 2 VTH VDD vIFloyd, Digital Fundamentals, 10th ed 77 反相输 出 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
78. 78. 30kΩ CMOS 反相器 10kΩ vo1 vI vo VDD = 15V v′ I G1 G2 ′ vo 输 入信号如下图  10  V vI/V VT + =  1 +  DD = 10V  30  2 15 10  10  V 5 VT − =  1 −  DD = 5V t  30  2 vo 输 出信号如右图 tFloyd, Digital Fundamentals, 10th ed 78 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
79. 79. 施密特触发 器的应 用 vI (1) 波形变 VT 换 V ＋ T- vI vo vO (2) 脉冲整形 Pulse conditioning v I VT V ＋ T-Floyd, Digital Fundamentals, 10th ed 79 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
81. 81. (4) 脉冲鉴 幅 Amplitude Checking vI vO ′ vI VT V ＋ T- vOFloyd, Digital Fundamentals, 10th ed 81 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
82. 82. 8-6 One-Shot 单稳态触发器 • One shot ( mono-stable multi-vibrator) only has one stable state and one unstable state. • When triggered the device changes from its stable state and remains there for a fixed period of time, known as the pulse width, before returning to its stable state.Floyd, Digital Fundamentals, 10th ed 82 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
83. 83. • The duration time of the unstable state determined by the circuit parameters, no related with the triggered pulse. Trigger Q tW • The duration time of the unstable state determines the pulse width of the output pulse.Floyd, Digital Fundamentals, 10th ed 83 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
84. 84. A Simple One-Shot +V 1 Trigger vI R 0 vI2 0 G1 G2 Q vO1 1 1 0 C V vI tW = RC ln Basic One-shot−Logic Symbols V VTH vO1 _ + = RC ln 2 vI2 ≈R <<R 0.7 RC VTH on  − t   uC = V (1 − e ) RC Q  Floyd, Digital Fundamentals, 10th ed 84 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
85. 85. • Stable state: Q=0 • Unstable state: Q=1 • The time duration determined by the charge time of C and R , i.e. the RC time constant. VDD tW = RC ln = RC ln 2 ≈ 0.69 RC VDD − VTH ≈ 0.7 RCFloyd, Digital Fundamentals, 10th ed 85 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
86. 86. +V Q REXT Trigger C EXT Q CX Q RX / CX Trigger Logic Symbol Q tW = 0.7 Rext CextFloyd, Digital Fundamentals, 10th ed 86 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
87. 87. Basic types of IC one-shot Nonretrigg Retriggera erable ble one-shot one-shotFloyd, Digital Fundamentals, 10th ed 87 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
88. 88. Non-retriggerable one-shot • Not respond to any additional trigger pulse from the time it is triggered until it returns to stable state. ignoredFloyd, Digital Fundamentals, 10th ed 88 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
90. 90. 74121: Schmitt-Trigger Inputs  This symbol indicates a Schmitt-trigger input. This type of input uses a special threshold circuit that produces hysteresis, a characteristic that prevents erratic switching between states when a slow-changing trigger voltage hovers around the critical input level.Floyd, Digital Fundamentals, 10th ed 90 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
91. 91. 74121: Nonretriggerable One-shot Schmitt-Trigger Inputs A1 1 A2 Q BVCC RINT RI CEXT CX Q RX/CX REXT/CEXT tW ≈ 30ns 内接一个 2kΩ 电 阻 ttW ≈0.7(2KΩ) CEXT W ≈0.7REXT CEXT tW=0.7RCEXT ： 30ns to 28s To achieve a one-shot with a pulse width of approximately 10ms, using a 74121. If select REXT=20KΩ, calculate the necessary capacitance ， and show the connection.Floyd, Digital Fundamentals, 10 ed th 91 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
92. 92. Retriggerable One-shots • A retriggerable one-shot can be triggered before it times out. retriggeredFloyd, Digital Fundamentals, 10th ed 92 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
93. 93. 74122: Retriggerable One-shot 内部是 10kΩ 电 阻 tW ≈ 45ns no external resistor and capacitor  0.7  tW = 0.32 RC EXT  1 +   R  With external resistor and capacitorFloyd, Digital Fundamentals, 10th ed 93 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
95. 95. Exercise: 0.7 tW = 0.32 RC EXT (1 + ) R 0.7 = 0.32 × 47 KΩ × 68µ F × (1 + ) 47 KΩ = 1.0227( s) ≈ 1( s)Floyd, Digital Fundamentals, 10th ed 95 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
96. 96. The 555 Timer • The 555 timer is a versatile and widely used device because it can be configured in three different modes as a Schmitt trigger, a one-shot, or an oscillator. • 555 定时器是一种将模拟电路和数字电 路集成于一体的电子器件。用它可以构 成施密特触发器、单稳态触发器、多谐 振荡器等多种电路。 555 定时器在工业 控制、定时、检测、报警等方面有广泛 96Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
97. 97. Comparator uo VI+ + - VO uI+-uI- VI- If VI+>VI-, then VO=HIGH If VI+<VI-, then VO=LOWFloyd, Digital Fundamentals, 10th ed 97 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
98. 98. 555 Timer 555 Threshold VI(control) Latch 2/3VCC Output 1/3VCC Output Trigger buffer Discharge Discharge Transisto rFloyd, Digital Fundamentals, 10th ed 98 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Reset
99. 99. Basic operation UCC 比较结 果 5KΩ 2/3UCC 悬空 + V6 V2 R SVref 6 R VA C1 <VA <VB 0 1 5 1/3UCC 5KΩ > VA >VB 1 0 VB + S <VA >VB 0 0 2 C1 > VA <VB 1 1 5KΩ Vref VA = Vref , VB = 2Floyd, Digital Fundamentals, 10th ed 99 © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
100. 100. Vcc Collector C If VBE>Vbias, Vc=LOW Base B If VBE<Vbias, Vc=HIGH E EmitterFloyd, Digital Fundamentals, 10th ed 100© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
101. 101. 555 定时 器的简 化功能表： Q RD R S Q Q uO T 1 1 0 0 1 0 导通 1 0 1 1 0 1 截止 1 1 1 1 1 0 导通 1 0 0 保持 保持 保持 保持 0 × × 0 1 0 导通 基本 S-R 锁 存器功能表Floyd, Digital Fundamentals, 10th ed 101© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
102. 102. 555 Timer–one shot? 555 Threshold VI(control) Latch 2/3VCC Output 1/3VCC Output Trigger buffer Discharge Discharge Transisto rFloyd, Digital Fundamentals, 10th ed 102© 2009 Pearson Education,Reset River, NJ 07458. All Rights Reserved Upper Saddle
105. 105. Before Triggering R1 555 0 1 0 0.01µF 0Trigger 1 0V on C1Floyd, Digital Fundamentals, 10th ed 105© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 1
106. 106. When Triggered R1 555 0 0.01µFTrigger VC1 C1 off chargingFloyd, Digital Fundamentals, 10th ed 106© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved 1
107. 107. At the end of charging interval R1 555 0.01µF 0Trigger 12/3VCC VC1 C1 0 discharging Floyd, Digital Fundamentals, 10 ed th 107© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
109. 109. t0 = 0 VCC tW = t1 − t0 = t1 dVC1 (t ) R1C1 + VC1 (t ) = VCC dt R1 VC1 (t ) = VC1 (∞) + [VC1 (0) − VC1 (∞)]e −t / R1C1 VC1 (t ) −t / R1C1 VC1 (∞) − VC1 (t ) e = C1 VC1 (∞) − VC1 (0) VC1 (∞) − VC1 (0) t = R1C1 ln VC1 (∞) − VC1 (t ) v(∞) − v(0) VCC − 0 tW = t1 = R1C1 ln = R1C1 ln = R1C1 ln 3 ≈1.1R C1 1 v(∞) − v(t1 ) VCC − 3 VCC 2Floyd, Digital Fundamentals, 10th ed 109© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
110. 110. Example For C1=0.01µF, determine the value of R1 for a pulse width of 1ms. −3 tW 1 × 10 R1 = = −6 ≈ 91KΩ 1.1C1 1.1 × 0.01 × 10Floyd, Digital Fundamentals, 10th ed 110© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
115. 115. charging R1 555(R1+R2)C1 1 R2 0 1 2 0Vc1 = VCC c1 3 C1 Floyd, Digital Fundamentals, 10th ed 115© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
116. 116. R1 555 R2C1 0 R2 1 2 1V 1Vc1 < CCVc1 = VCC 33 + C1 -discharging Floyd, Digital Fundamentals, 10th ed 116© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
117. 117. Vc 2 VCC 3 1 VCC 3 Vo T tL tHFloyd, Digital Fundamentals, 10th ed 117© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
118. 118. Calculation t H = 0.7( R1 + R2 )C1 T = 0.7( R1 + 2 R2 )C1 1.44 f= t L = 0.7 R2C1 ( R1 + 2 R2 )C1 R1 + R2 Duty cycle = × 100% R1 + 2 R2Floyd, Digital Fundamentals, 10th ed 118© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
122. 122. Calculation t H = 0.7 R1C1 T = 0.7( R1 + R2 )C1 1.44 f= t L = 0.7 R2C1 ( R1 + R2 )C1 R1 Duty cycle = × 100% R1 + R2Floyd, Digital Fundamentals, 10th ed 122© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
123. 123. Exercise A circuit need a 1Hz clock signal with a duty cycle of 2/3. R1=40kΩ, C=10µF. Determine the value of R2. (1) Using the first connection of 555 timer. (2) Using the second connection of 555 timer.Floyd, Digital Fundamentals, 10th ed 123© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
127. 127. Any Duty Cycle t H = R1C1 ln 2, t L = R2C1 ln 2, T = ( R1 + R2 )C1 ln 2 R1 D = tH / T = 100% R1 + R2Floyd, Digital Fundamentals, 10th ed 127© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
128. 128. uI2 VCC313 VCC 555 0 tuO 0.01µF VO VI 0 tvI < 1 VCC → vC1 = 1, vC 2 = 0 → Q = 1 → vO = 1 313 VCC < vI < 2 VCC → vC1 = vC 2 = 1 → Q = 1 → vO = 1 3vI > 2 VCC → vC1 = 0, vC 2 = 1 → Q = 0 → vO = 0 3 Floyd, Digital Fundamentals, 10th ed 128© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
129. 129. UT+ uI 2 vO 1 3 VCC → VCC ← ΔUT 3 1 VCC 3 O t UT- uO O 1 2 vI O VCC VCC t 3 3 Note: if control voltage VCO (PIN 5) is given, then UT+ = VCO UT- = 1/2VCO ΔUT- = 1/2VCOFloyd, Digital Fundamentals, 10th ed 129© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
130. 130. Voltage Transfer Characteristic VT − = 1 VCC 3 VT + = 2 VCC 3 VT + − VT − = 1 VCC 3Floyd, Digital Fundamentals, 10th ed 130© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
132. 132. Summary • Bistable – Latch – Trigger • One-shot • 555 Timer – One-shot – Astable – Schmitt-TriggerFloyd, Digital Fundamentals, 10th ed 132© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
133. 133. Selected Key Terms Latch A bistable digital circuit used for storing a bit. Bistable Having two stable states. Latches and flip-flops are bistable multivibrators. Clock A triggering input of a flip-flop. D flip-flop A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse. J-K flip-flop A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes.Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
134. 134. Selected Key Terms Propagation The interval of time required after an input signal delay time has been applied for the resulting output signal to change. Set-up time The time interval required for the input levels to be on a digital circuit. Hold time The time interval required for the input levels to remain steady to a flip-flop after the triggering edge in order to reliably activate the device. Timer A circuit that can be used as a one-shot or as an oscillator.Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
135. 135. 1. The output of a D latch will not change if a. the output is LOW b. Enable is not active c. D is LOW d. all of the aboveFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
136. 136. 2. The D flip-flop shown will Q a. set on the next clock pulse D b. reset on the next clock pulse CLK CLK c. latch on the next clock pulse Q d. toggle on the next clock pulseFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
137. 137. 3. For the J-K flip-flop shown, the number of inputs that are asynchronous is PRE a. 1 b. 2 J Q c. 3 CLK Q d. 4 K CLRFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
138. 138. 4. Assume the output is initially HIGH on a leading edge triggered J-K flip flop. For the inputs shown, the output will go from HIGH to LOW on which clock pulse? a. 1 CLK b. 2 J c. 3 K 1 2 3 4 d. 4Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
139. 139. 5. The time interval illustrated is called a. tPHL 50% point on triggering edge b. tPLH CLK c. set-up time Q 50% point on LOW-to- d. hold time HIGH transition of Q ?Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
140. 140. 6. The time interval illustrated is called a. tPHL b. tPLH D CLK c. set-up time d. hold time ?Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
141. 141. 7. The application illustrated is a a. astable multivibrator HIGH HIGH b. data storage device fout J QA J QB c. frequency multiplier fin CLK CLK d. frequency divider K KFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
142. 142. Output lines Q0 8. The application illustrated is a D C a. astable multivibrator R D Q1 b. data storage device C R c. frequency multiplier D Q2 d. frequency divider C Parallel data input lines R D Q3 Clock C R ClearFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
143. 143. 9. A retriggerable one-shot with an active HIGH output has a pulse width of 20 ms and is triggered from a 60 Hz line. The output will be a a. series of 16.7 ms pulses b. series of 20 ms pulses c. constant LOW d. constant HIGHFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
144. 144. 10. The circuit illustrated is a +VCC a. astable multivibrator (4) (8) R1 b. monostable multivibrator (7) RESET VCC DISCH c. frequency multiplier R2 (6) THRES OUT (3) (2) (5) d. frequency divider C1 TRIG CONT GND (1)Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved © 2008 Pearson Education
145. 145. Answers: 1. b 6. d 2. d 7. d 3. b 8. b 4. c 9. d 5. b 10. aFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved