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Shift registers

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shift register

shift register

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  • 1.   After learning this chapter, students should be able to;   Identify the basic forms of data movement in shift registers.   Explain how serial in/serial out (SISO), serial in/parallel out (SIPO), parallel in/serial out (PISO) and parallel in/parallel out (PIPO) shift registers operate.   Determine how bidirectional shift register operates.   Analyze output waveform for general shift register and 74HC195 shift register IC.   Construct Johnson and ring counters from shift register.   Describe shift register applications such as time delay, serial to parallel converter, universal asynchronous receiver transmitter (UART) and keyboard encoder. 1 2  Register – one or more flip-flops used to store or hold data.  Shift register has 2 basic functions such as;  Shift registers ◦  Data storage-  A group of flip-flops used to shift/transfer data from flip-flop to flip-flop. ◦  Data movement-  a group of D flip-flops connected in a chain and the clock of the flip-flops is connected in a synchronous manner.  Shift register has 4 classifications namely;-  They are generally provided with a Clear or Reset connection so that they can ◦  Serial in/serial out (SISO) be "SET" or "RESET" as required. ◦  Serial in/parallel out (SIPO)-  Shift registers are available in IC form or can be constructed from discrete ◦  Parallel in/serial out (PISO) flip-flops. ◦  Parallel in/parallel out (PIPO) 3
  • 2.   The storage capacity is the total number of bits of   Shift capability permits data movement within the register or into or out of the digital data it can retain. The total number of bits register when trigger by clock pulse depend on the number of flip-flops being used.   For example, various data movement of four 4-bit registers with direction indicated by arrows  Storage capability make it important type of memory devices Data in  For example,   When 1 is applied to D flip-flop, its output Data in Data out Data out Data in Data out becomes 1 at the triggering edge of clock   The output remains 1 until next trigger Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out   Therefore, 1 is stored Data in  Next, Data in   When 0 is applied to D flip-flop, its output becomes 0 at the triggering edge of clock Rotate right Rotate left   The output remains 0 until next trigger Data out Data out   Therefore, 0 is stored Serial in/parallel out Parallel in/parallel out 5 6   The serial in/serial out shift register accepts data serially – that is, one bit at a time on a single line. Example: 5-bit serial-in serial-out register.   It produces the stored information on its output also in serial form. Each clock pulse will move an input bit to the next flip-   Example of IC: 74HC165, 74HC195 flop. For example, a 1 is shown as it moves across.   Each clock pulse will move an input bit to the next flip-flop. Figure 1 shows 5- bit SISO shift register. 1 1 1 1 1 1 Figure 1 CLK CLK 7
  • 3. Example: To shift 1011 in a 4-bit serial-in serial-out register starting with LSB. The register is initially reset. Timing diagram for 1011 in a 4 bit SISO Q0 Q1 Q2 Q3 1st clock pulse 2nd clock pulse 3rd clock pulse 4th clock pulse 5th clock pulse After 8th clock pulses, the register is CLEAREg: To shift 101 starting with LSB   4th clock, the 1st bit is shifted out, shift  Initially, all FF are being RESET. register contain 010 Q2Q1Q0=000  1st clock, shift register contains Q2Q1Q0=001   5th clock, the 2nd bit is shifted out, shift  2nd clock, shift register contains 010 register contains 100   6th clock, the 3rd bit is shifted out, shift  3rd clock, shift register contains 101, all 3- register is CLEAR bit input have been completely stored 11 12
  • 4. Exercise 1 (SISO)-Tutorial 4 no.6  Timing waveform for 3-bit SISO shift register   Show the states of the 5-bit register for the specified data input and clock waveforms. Assume that the register is initially cleared (all 0s). Show the states of the 5-bit register in Figure 4.6 for the specified data input and clock waveforms. Assume that the register is initially cleared (all 0s). Figure 4.6 13 Answer Exercise 1 Exercise 2 (SISO)-Tutorial 4 no.7 Show the states of the 4-bit register (SRG 4) for the data input and clock waveforms in Figure 4.7. The register initially contains all 1s. Figure 4.7 Data bits CLEAR after 10 clock pulses
  • 5. Answer Exercise 2   Data bits are entered serially (LSB first) in a SIPO shift register in the same manner as SISO. Example of IC: 74HC164, 74HC195   The difference is the way in which the data bits are taken out of the register; in the parallel output register.   Data bits are taken out in parallel   Once all bits are store, the bits are shifted out simultaneously   Example, Figure 2 shows 4-bits SIPO shift register Data bits CLEAR after 8 clock pulses Figure 2 18An application of shift registers is conversion of serialdata to parallel form.For example, assume the binary number 1101 is loadedsequentially, one bit at each clock pulse.After 4 clock pulses, the data is available at the parallel output. CLK 20
  • 6. Exercise 1 (SIPO)  Example: Timing waveform for 4-bit SIPO shift register when data bits 0110 Show the states of the 4 bit register (SRG 4) for the data input is entered. The register initially contains all 1’s. and clock waveforms in the figure below. The register initially contains all 0’s. (LSB) (LSB) 21 Answer Exercise 1 (SIPO)   Data bits are entered parallel on the same time and data bits are shifted out in a single line. Example of IC: 74HC165, 74HC195.   D0, D1, D2 and D3 are parallel inputs where, D0 is MSB and D3 is LSB.   Example, Figure 3 shows 4-bits PISO shift register.   To write data in, the mode control line is taken to LOW and the data is clocked in. The data can be shifted when the mode control line is HIGH as SHIFT is active high. D0 D1 D2 D3 SHIFT/LOAD Serial data out Figure 3 CLK 24
  • 7.   Example: Timing waveform for 4-bit PISO shift register when data bits D0D1D2D3 = 0101 is entered. Assume D input remains a 1. Write = Load, initial state = 0000, assume D input remains a 1 25 Exercise 1 (PISO)-Tutorial 4 no.8 Answer Exercise 1 Show the data output waveform for a 4-bit register with the parallel input data and the clock and SHIFT / LOAD waveforms. The register initially contains all 0’s. Assume the D input remains a 0. Figure 4.8
  • 8.   Example of IC: 74HC195   Capable to shift data bits either left or right. Example of IC: 74HC194  Data bits are entered parallel on the same time   Use gate logic that enables the transfer of a data bit a stage to the next stage to  Data bits are shifted out parallel on the same time the left or right.  Example, Figure 4 shows 4-bits PIPO shift register inserted with D0=1, D1=0, D2=1 and   Example, Figure 5 shows 4-bit bidirectional shift register. D3=0.   If the signal RIGHT/LEFT is 1, serial data bits will enter into FF0 and move to the right , otherwise it will be entered into FF3 and move to the left. Figure 4 29 Figure 5 30  Example: Timing waveform for 4-bit bidirectional assume that initial value for Q0 = 1, Q1 = 1, Q2 = 0 and Q3 = 1 and the serial data-input line is LOW. 1.  An 8 bit serial in/parallel out shift register 74HC164  SIPO 2.  An 8 bit parallel load shift register 74HC165  PISO, SISO 3.  A 4 bit parallel access shift register 74HC195  PIPO, SISO, SIPO and PISO. 4.  A 4 bit bidirectional universal shift register 74HC194  bidirectional shift register # Try the exercise on page 165 31
  • 9. A 4 bit parallel access shift register(74HC195)   74HC1945 block diagram The 74HC195 4 bit parallel-access shift register. (refer to page 493)   The 74HC195 can be used for PIPO operation.   It also has a serial input, so it can be used   When SH/LD’ is LOW, the data on the parallel inputs are entered synchronously on the positive transition of the clock. for SISO and SIPO operations.   When SH/LD’ is HIGH, stored data will shift right (Q0 to Q3) synchronously with the clock.   It can be used for PISO operation by   Inputs J and K’ are the serial data inputs to the first stage of the register (Q0). Q3 can be used for serial output data. using Q3 as an output.   The active-LOW clear input is asynchronous. 33 34   For the 74HC195 4 bit shift register shown in Figure 1, determine all the output of Q in Figure 2. Assume register is initially clear. (Page 172) Figure 1 35 36
  • 10. Answer Exercise (74HC195) Figure 2 37   Known as twisted ring counter, switch tail counter or binary counter.  A shift register counter is basically a shift register with the serial output connected back to the serial input to produce special sequences.   Produce 2n modulus counter where n is the number of bits.  These devices are often classified as counters because they exhibit a 2n = number of stages specified sequence of states.  Shift registers can form useful counters by recirculating a pattern of 0’s and Eg: mod-10 Johnson counter has 10 stages, so there are 5 ffs in this 1’s. Two important shift register counters are: counter. 1. Johnson counter 2. Ring counter.   The complement of the last flip-flop is feedback to the input of first flip-flop   The Johnson counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states (2n, where n = number of bits).   Can use D and JK flip-flop but not T flip-flop. 39 40
  • 11.   For example, 4-bit Johnson counter using D flip-flop 2n = 2 x 4 = 8 stages   Mod-8 Johnson counter / 4 bit Johnson counter (8 stages) The Johnson counter can be made with a series of D flip-flops … or with a series of J-K flip Figure: 4 bit Johnson sequence flops. Here Q3 and Q3 are fed back to the J and K inputs with a “twist”. 41 42  Timing waveform for 4-bit Johnson counter Johnson counter Redrawing the same Johnson counter (without the clock shown) illustrates why it is sometimes called as a “twisted- ring” counter. 0 1 “twist” 0 0 0 0 0 0 43
  • 12.   Example 2: 5 bit Johnson counter / mod-10 Johnson counter 2n = 2 x 5 = 10 stages   Using D flip-flops with negative-going triggered (NGT) clock, draw a circuit diagram including timing diagram for a MOD-12 Johnson counter with an initial state of all “0’s”. Figure: 5 bit Johnson sequence 45 46   The ring counter   Mod-12 counter has 12 stages (clock pulse: 1 12)   Produce n modulus counter where n is the number of stages   2n = 12 ; n = 6 flip-flops   The last stage is feedback to the input of first flip-flop   The ring counter can also be implemented with either D flip-flops or J-K flip- flops. Here is a 4-bit ring counter constructed from a series of D flip-flops. Notice the feedback. Like the Johnson counter, it can also be implemented with J-K flip flops. 47 48
  • 13.   For example, 4-bit ring counter using D flip-flop 4 bit ring counter   Initially, FF0 is set while the others are cleared Figure: 4 bit Ring sequence The initial value is Q0 = 1, Q1 = 0, Q2 = 0 and Q3 = 0 49 50  Timing waveform for 4-bit ring counter which initially reset all flip-flop Advantage of ring counter except FF0   A ring counter requires more flip-flops than a johnson counter for the same MOD number. For example, a MOD-8 ring counter requires 8 flip-flops while a MOD-8 johnson counter only requires 3 (23 = 8). So if a ring counter is less efficient in the use of flip-flops than a johnson counter, why do we still need ring counters?   One main reason is because ring counters are much easier to decode. In fact, ring counters can be decoded without the use of logic gates. The decoding signal is obtained at the output of its corresponding flip-flop. Disadvantage of ring counter   It is not "self starting". Have to press preset button.   More flip-flop than johnson counter 51 52
  • 14. Ring counter Redrawing the Ring counter (without the clock shown) shows why it is a “ring”. The disadvantage to this counter is that it must be preloaded with the desired pattern (usually a single 0 or 1) and it has even fewer states than a Johnson counter (n, where n = number of Johnson counter with decoding circuit flip-flops. On the other hand, it has the advantage of being self-decoding with a unique output for each state. 53 1.  Time delay (for SISO) 2. Serial to parallel converter   Shift registers such as SISO can be used to delay a digital signal by a   Serial data transmission is widely used by peripherals to pass data predetermined amount. back and forth to a computer.   The time delay can also be increased by cascading shift registers.   Serial data transmission from one digital system to another is Example: commonly used to reduce the number of wires in the transmission line. An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register?   However, all computers process data in parallel form. Therefore, a Solution: serial to parallel converter is required.   To connect peripheral devices, serial port has largely beenThe delay for each clock replaced by USB. USB (Universal Serial Bus) is used to connectis 1/40 MHz = 25 ns keyboards, printers, scanners to the computer.   USB was designed as a high-speed serial bus which could efficiently The total delay is interconnect peripherals such as hard disks, audio interfaces, and 8 x 25 ns = 200 ns video equipment. 55 56
  • 15. 3. Universal Asynchronous Receiver Transmitter (UART) 4.  Keyboard Encoder   A piece of computer hardware that translate data between parallel and   The keyboard encoder is an example of where a serial forms.   A microchip with programming that controls a computer’s interface to ring counter is used in a small system to encode a its attached serial devices. key press.   A UART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial   Two 74HC195 shift registers are connected as an port. UARTs are now commonly included in microcontrollers. 8-bit ring counter preloaded with a single 0. As the 0 circulate in the ring counter, it “scans” the keyboard looking for any row that has a key closure. When one is found, a corresponding column line is connected to that row line. MAX232 is a voltage converter to convert -8V/8V from PC to 5V microcontroller or   The combination of the unique column and row either way. lines identifies the key. The schematic is shown on UART is a data format converter to convert from serial to parallel data (External device to PC) or parallel to serial data (PC to external device). the following slide… 57 58 1. The shift register that would be used to delay serial data by 4 clock periods is a. c. b. d.
  • 16. 2. The circuit shown is a 3. If the SHIFT/LOAD line is HIGH, data a. serial-in/serial-out shift register a. is loaded from D0, D1, D2 and D3 immediately b. serial-in/parallel-out shift register b. is loaded from D0, D1, D2 and D3 on the next CLK c. parallel-in/serial-out shift register c. shifted from left to right on the next CLK d. parallel-in/parallel-out shift register d. shifted from right to left on the next CLK4. A 4-bit parallel-in/parallel-out shift register will store data for 5. The 74HC164 (shown) has two serial inputs. If data is placed on the a. 1 clock period A input, the B input b. 2 clock periods a. could serve as an active LOW enable b. could serve as an active HIGH enable c. 3 clock periods c. should be connected to ground d. 4 clock periods d. should be left open CLR CLK Serial A inputs B Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
  • 17. 6. An advantage of a ring counter over a Johnson counter is that the ring 7. A possible sequence for a 4-bit ring counter is counter a. … 1111, 1110, 1101 … a. has more possible states for a given number of flip-flops b. … 0000, 0001, 0010 … b. is cleared after each cycle c. … 0001, 0011, 0111 … c. allows only one bit to change at a time d. … 1000, 0100, 0010 … d. is self-decodingFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Reserved 8. The circuit shown is a 9. Assume serial data is applied to the 8-bit shift register a. serial-in/parallel-out shift register shown. The clock frequency is 20 MHz. The first data bit b. serial-in/serial-out shift register will show up at the output in c. ring counter a. 50 ns d. Johnson counter b. 200 ns c. 400 ns d. 800 nsFloyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
  • 18. 10. For transmission, data from a UART is sent in a. asynchronous serial form b. synchronous parallel form c. can be either of the above d. none of the above