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Serial peripheral interface..

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  • 1. Serial Peripheral Interface
  • 2. What is SPI?o Serial Bus protocolo Fast, Easy to use, Simpleo Everyone supports ito A communication protocol using 4 wireso Also known as a 4 wire buso Used to communicate across small distanceso Multiple Slaves, Single Mastero Synchronizedo Full Duplex
  • 3. Protocol Wires: Master Out Slave In (MOSI)‫‏‬ Master In Slave Out (MISO)‫‏‬ System Clock (SCLK)‫‏‬ Slave Select 1…N Master Set Slave Select low Master Generates Clock Shift registers shift in and out data
  • 4. Wires in Detail MOSI – Carries data out of Master to Slave MISO – Carries data from Slave to Master(Both signals happen for every transmission) SS_BAR – Unique line to select a slave SCLK – Master produced clock to synchronizedata transfer
  • 5. Master shifts out data to Slave, and shift in data from Slave
  • 6. Serial Peripheral Interface (SPI)Data is shifted out of the masters MOSI pin and in its MISO pinData transfer is initiated by simply writing data to the SPI data register.All data movement is coordinated by SCK.Slave select may or may not be used depending on interfacing device.slave SPI devicemaster SPI device
  • 7. Master and multiple independent slaves
  • 8. Master and multiple daisy-chained slaves
  • 9. Data Transmission Mode
  • 10. data order: if set, LSB istransmitted firstinterrupt enable: if set, interruptoccurs when SPI interrupt flagand global interrupt enable are setspi enable: if set, SPI interfaceis enabledmaster/slave select: if set,SPI in master modeclock polarity:0 SCK low in idle1 SCK high in idleclock phase:0 leading edge sample, trailing edge setup1 leading edge setup, trailing edge sampleclock rateSPI2X SPR1 SPR0 SCLK0 0 0 fosc/40 0 1 fosc/160 1 0 fosc/640 1 1 fosc/1281 0 0 fosc/21 0 1 fosc/81 1 0 fosc/321 1 1 fosc/64(in SPSR)SPI Control Register (SPCR)
  • 11. interrupt flag: set when serialtransfer is completewrite collision: set if SPDR iswritten during a receive transfer2x clock rate: if set, doublesclock rate in master modereserved bitsSPI Status Register (SPSR)
  • 12. SPI Data Register (SPDR)SPDR is a read/write register used for data transfer.Writing SPDR sends data out MOSI.Reading SPDR gets the data that was clocked into MISO.
  • 13. Configuration SPI can be configured as MASTER or SLAVE Here is described how to configure inMASTER/SLAVE
  • 14. The following sequence describes howone should process a data transfer withthe SPI block when it is set up to be themaster.The process assumes that any priordata transfer has already completed.Configuration-MASTER operation
  • 15. Configuration-MASTER operation1. Set the SPI clock counter register to thedesired clock rate.2. Set the SPI control register to the desiredsetting.3. Write the data to transmit to the SPI dataregister . This write starts the SPI datatransfer.
  • 16. Configuration-MASTER operation4. Wait for the SPIF bit in the SPI statusregister to be set 1 . The SPIF bit willbe set after the last cycle of SPI datatransfer .5. Read the SPI status register.
  • 17. 6. Read the received data from the SPIdata register(optional).7. Go to step 3 if more data is requiredtransmit .Configuration-MASTER operation
  • 18.  A read or write of the SPI data register isrequired in order to clear the SPIF status bit. Therefore , if the optional read of the SPIdata register does not take place ,a write tothis register is required in order to clear theSPIF status bitConfiguration-MASTER operationNote:
  • 19.  The following sequence describes how oneshould process a data transfer with the SPIblock when it is set up to be the SLAVE. The process assumes that any prior datatransfer has already completed.Configuration-SLAVE operation
  • 20. 1. Set the SPI control register to the desiredsettings.2. Write the data to transmit to the SPI dataregister .Note : This can only be done whena slave SPI data transfer is not in progress.Configuration-SLAVE operation
  • 21. 3. Wait for the SPIF bit in the SPI statusregister to be set 1 . The SPIF bit will be setafter the last sampling clock edge of SPIdata transfer .4. Read the SPI status register.Configuration-SLAVE operation
  • 22. Configuration-SLAVE operation5. Read the received data from the SPI dataregister(optional).6. Go to step 2 if more data is requiredtransmit .
  • 23. Configuration-SLAVE operationNote: A read or write of the SPI data register is requiredin order to clear the SPIF status bit. Therefore , at least one of the optional reads orwrites of the SPI data register must take place ,inorder to write to clear the SPIF status bit
  • 24. Pros and Cons:Pros: Fast and easy Fast for point-to-point connections Easily allows streaming/Constant data inflow No addressing/Simple to implement Everyone supports itCons: SS makes multiple slaves very complicated No acknowledgement ability No inherent arbitration No flow control