Nmos and cmos fabrication


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Nmos and cmos fabrication

  3. 3. 3Create N-well(for PMOS devices) &Channel Stop RegionsGrow Field &Gate OxideDeposit & PatternPoly LayerImplant S, D &Substrate ContactsCreate ContactWindowsDeposit & PatternMetal LayerImpurity Implant Into The Substrate.Thick Around The nMOS And pMOS ActiveRegions And Thin Respectively ThroughThermal Oxidation.Creation Of n+ And p+ Regions.Metallization
  4. 4. 4PHOTOLITHOGRAPHY• IC Is Set Of Patterned Layers OfDoped Silicon, Polysilicon, Metal AndSiO2.• All Areas Are To Be Defined ByProper Masks.• A Layer Must Be Patterned BeforeAnother Is Applied On The Chip.• Every Layer Will Undergo LithographyWith Different Mask.Si SubstrateSiO2 layer by thermal oxidationUnpatterned StructureSi SubstrateSiO2SiO2Patterned StructurePhotolithography
  5. 5. 5Si SubstrateSi Substrate5-200 nm SiO2layer by thermaloxidationSi SubstrateLight Sensitive,Acid Resistantcompound= PhotoresistSi SubstrateUV LightInsoluble PhotoresistSoluble PhotoresistvGlass MaskSi SubstrateHardened PhotoresistChemical or Dry EtchSi SubstrateHardened PhotoresistSiO2 Windowreaching down toSi substrateSi SubstrateHardened photoresist removed by stripping solvents.Obtained Patterned SiO2feature on the Si SubstrateFor High Density Patterns Required In SubMicron Devices, E-beam Lithography Is UsedInstead Of Optical Lithography.
  6. 6. 6Fabrication of nMOS: Basic stepsSi SubstrateSi SubstrateThick Oxidelayer(field oxide)Si SubstrateSi SubstrateThin highquality OxideLayer(gate oxide)OXIDATIONSELECTIVE ETCHING FOR DEFININGACTIVE AREA ON WHICH MOSFETWILL BE FABRICATEDSi SubstrateDeposition of polysilicon(gate + interconnect medium)Si SubstratePatterned and etchedpolysilicongate oxideoxide
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  8. 8. 8Si SubstratePatterned and etchedpolysilicongate oxideoxideFabrication of nMOS: Basic stepsBare Si surface toform S & Dpolysilicongate oxideoxiden+ n+n+ n+Doping : Diffusion orion implantation(high concentration ofimpurity atoms)Insulating oxiden+ n+Patterned and etchedContact windows forD & S
  9. 9. 9Fabrication of nMOS: Basic stepsn+ n+n+ n+EvaporatedAluminumPatterned and etchedMetal contactsBy creating anotherinsulating oxide layer,cutting contact holes (via),depositing and patterningmetal, two more layers ofmetallic interconnects canalso be added on the top ofthis structure.
  10. 10. 10• Electrical isolation on a single chip containing manydevices is necessary• To prevent undesired conducting paths;• To avoid creation of inversion layers outside thechannels;• To reduce leakage currents.CHALLENGES:
  11. 11. 11I) ETCHED FIELD OXIDE ISOLATION:Devices are created in dedicated regions called activeareas.Each active area is surrounded by thick oxide barriercalled field oxide.Thick oxide is grown on complete surface of the chip andthen selectively etched to define active areas.Straight forward method.Thickness of oxide leads to large oxide steps at theboundaries of active areas and isolation regions.May lead to chip failure due to cracking of depositedlayers due to large height difference at the boundaries.DEVICE ISOLATION TECHNIQUES:
  12. 12. 12DEVICE ISOLATION TECHNIQUES:II Local oxidation of silicon
  13. 13. 13LOCOS technique is based on theprinciple of selectively growingthe field oxide in certainregions , instead of selectivelyetching away active areas afteroxide growth.For selective growth of oxide,active areas are covered withSilicon nitride.
  14. 14. 14DEVICE ISOLATION TECHNIQUES:LOCOSSi SubstrateSi3N4Thin PAD OXIDE(stress relief oxide)Protects Si surface from stress caused by nitrideduring subsequent process steps.(Patterned and etched)(Doping of exposed Si surface with p type impurity)Si Substratep+ p+p+Si3N4Si3N4Isolation Regions(Channel stop implants)Si Substrate
  15. 15. 15Si Substratep+p+ p+Lateral extension under nitride layerSi3N4 Si3N4Thick Field Oxide which partiallyrecesses into Si substrateBird’s beak** Reduces active areaSi Substratep+p+ p+THE ACTIVE AREAS(Patterned and etched)LOCOS is popular :More planar surface topologyBird’s beak encroachment canbe reduced up to some limitby device scaling
  16. 16. 16III) MULTILEVEL INTERCONNECTS & METALLIZATION:• 4 to 8 metal layers are used to create interconnections betweenthe transistors and for routing the power supply, signal lines andclock lines on the chip surface.• Allows higher integration densities.• Adds to the third dimension.• Electrical connections between the layers are made by vias.• Each via is formed by creating an opening in isolation oxidebefore every metallization step and filling it with a special metalplug (Tungsten).• After creation of via, new metal layer is deposited andsubsequent patterning is done.DEVICE ISOLATION TECHNIQUES:
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  21. 21. 21SOME FACTS:• Due to various process steps chip surface is highlynonplanar.• . It may inhibit local thinning and discontinuities at unevensurface edges• Deposition of multiple metal interconnect lines is notdesirable on such irregular topography.• They will lead to hills and valleys on the chip surface.• Hence surface is usually planarised before every newmetal deposition step.• For this, a fairly thick SiO2 layer is grown on the wafersurface to cover all existing surface nonuniformities.• Its surface is then planarised by any one of:Glass reflow (heat treatment),Etch back,Chemical mechanical polishing (CMP).CMP: Actual polishing of wafer surface using abrasive silicaslurry.Adopted in recent years.
  22. 22. 22EXERCISE:*Epitaxial layer** Difference between ionimplantation and diffusion processesof doping.*** Design masks for all patterningand etching steps in the fabricationof nMOS transistor for positive andnegative photoresist material.