lowpower
Upcoming SlideShare
Loading in...5
×
 

lowpower

on

  • 434 views

 

Statistics

Views

Total Views
434
Views on SlideShare
434
Embed Views
0

Actions

Likes
0
Downloads
11
Comments
0

0 Embeds 0

No embeds

Accessibility

Categories

Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

lowpower lowpower Presentation Transcript

  • Session 2: Power Basic, Logic Power, Low Power Design By A.D.Darji, Assistant Professor [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.] 9/30/2010 VLSI Design Lab,SVNIT
  • Why Power Matters • • • • • • Packaging costs Power supply rail design Chip and system cooling costs Noise immunity and system reliability Battery life (in portable systems) Environmental concerns 9/30/2010 VLSI Design Lab,SVNIT
  • Where is Power Dissipated in CMOS? • Active (Dynamic) power – (Dis)charging capacitors – Short-circuit power • Both pull-up and pull-down on during transition • Static (leakage) power – Transistors are imperfect switches • Static currents – Biasing currents 9/30/2010 VLSI Design Lab,SVNIT View slide
  • Why worry about power? -- Power Dissipation Lead microprocessors power continues to increase 100 Power (Watts) P6 Pentium ® 10 8086 286 1 4004 8008 486 386 8085 8080 0.1 1971 1974 1978 1985 1992 2000 Year Power delivery and dissipation will be prohibitive 9/30/2010 VLSI Design Lab,SVNIT Source: Borkar, De Intel View slide
  • Why worry about power? -- Chip Power Density Sun’s Power Density (W/cm2) 10000 Surface Rocket Nozzle 1000 100 8086 Hot Plate 10 4004 8008 8085 386 286 8080 1 1970 9/30/2010 …chips might become hot… Nuclear Reactor 1980 P6 Pentium® 486 1990 Year 2000 VLSI Design Lab,SVNIT 2010 Source: Borkar, De Intel
  • Chip Power Density Distribution Al-SiC+ Epoxy Die Attach Willamette Power Power Map Distribution On-Die Temperature 250 100 200-250 150-200 100-150 50-100 0-50 50 100 80 60 0 100-120 120 40 Temperature (C) 150 Heat Flux (W/cm2) 200 • Power density is not uniformly distributed across the chip • Silicon is not a good heat conductor • Max junction temperature is determined by hot-spots – Impact on packaging, w.r.t. cooling 60-80
  • Why worry about power ? -- Battery Size/Weight 50 Battery (40+ lbs) Nominal Capacity (W-hr/lb) Rechargable Lithium 40 Ni-Metal Hydride 30 20 Nickel-Cadmium 10 0 65 70 75 80 85 90 95 Year Expected battery lifetime increase over the next 5 years: 30 to 40% Note small improvement per year in battery power compared to improvements in processor complexity & speed 9/30/2010 VLSI Design Lab,SVNIT
  • Why worry about power? -- Standby Power Year 2005 2008 2011 2014 Power supply Vdd (V) Threshold VT (V) 1.5 0.4 1.2 0.4 0.9 0.35 0.7 0.3 0.6 0.25 Drain leakage will increase as VT decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption. 8KW 50% …and phones leaky! 1.7KW 40% Standby Power  2002 30% 20% 400W 88W 12W 10% 0% 2000 2002 2004 2006 2008 Source: Borkar, De Intel
  • Power and Energy Figures of Merit • Power consumption in Watts – It is the arte at which energy is delivered or exchanged – determines battery life in hours • Peak power – determines power ground wiring designs – sets packaging limits – impacts signal noise margin and reliability analysis • Energy efficiency in Joules – rate at which power is consumed over time • Energy = power * delay – Joules = Watts * seconds – lower energy number means less power to perform a computation at the same frequency 9/30/2010 VLSI Design Lab,SVNIT
  • Charging Capacitors Applying a voltage step E01  CV 2 R 1 E R  CV 2 2 V C Value of R does not impact energy! 1 EC  CV 2 2
  • Applied to Complementary CMOS Gate V dd PMOS A1 AN 2 E 01  CLVDD iL ER  NETWORK 1 2 CLVDD 2 V out NMOS CL EC  1 2 CLVDD 2 NETWORK • One half of the power from the supply is consumed in the pullup network and one half is stored on CL • Charge from CL is dumped during the 10 transition • Independent of resistance of charging/discharging network 9/30/2010 VLSI Design Lab,SVNIT
  • Power versus Energy Power is height of curve Watts Lower power design could simply be slower Approach 1 Approach 2 time Watts Energy is area under curve Two approaches require the same energy Approach 1 Approach 2 time 9/30/2010 VLSI Design Lab,SVNIT
  • PDP and EDP • Power-delay product (PDP) = Pav * tp = (CLVDD2)/2  Energy-delay product (EDP) = PDP * tp = Pav * tp2   EDP is the average energy consumed multiplied by the computation time required takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption) Energy-Delay (normalized) – PDP is the average energy consumed per switching event (Watts * sec = Joule) – lower power design could simply be a slower design 15 energy-delay 10 energy 5 delay 0 0.5  allows one to understand tradeoffsLab,SVNIT better VLSI Design 9/30/2010 1 1.5 Vdd (V) 2 2.5
  • Understanding Tradeoffs  Which design is the “best” (fastest, coolest, both) ? Lower EDP b a c Clearly a is “better” than c and c is “better” than b, but how about b and d? Or a and d? d Constant EDP’s are the straight lines in the graph 1/Delay better
  • CMOS Energy & Power Equations E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD Ileakage f01 = P01 * fclock P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage Dynamic power 9/30/2010 Short-circuit power VLSI Design Lab,SVNIT Leakage power
  • Dynamic Power Consumption Power = Energy/transition • Transition rate = CLVDD2•f01 = CLVDD2•f• P01 = CswitchedVDD2•f • Power dissipation is data dependent – depends on the switching probability • Switched capacitance Cswitched= P01CL= aCL (a is called the switching activity) 9/30/2010 VLSI Design Lab,SVNIT
  • Lowering Dynamic Power Capacitance: Function of fan-out, wire length, transistor sizes Supply Voltage: Has been dropping with successive generations Pdyn = CL VDD2 P01 f Activity factor: How often, on average, do wires switch? 9/30/2010 VLSI Design Lab,SVNIT Clock frequency: Increasing…
  • Short Circuit Power Consumption Vin Isc Vout CL Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting. 9/30/2010 VLSI Design Lab,SVNIT
  • Short Circuit Currents Determinates Esc = tsc VDD Ipeak P01 Psc = tsc VDD Ipeak f01 • Duration and slope of the input signal, tsc • Ipeak determined by – the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. – strong function of the ratio between input and output slopes • a function of CL 9/30/2010 VLSI Design Lab,SVNIT
  • Impact of CL on Psc Isc  0 Vin Isc  Imax Vout Vin CL Vout CL Large capacitive load Small capacitive load Output fall time significantly larger than input rise time. Output fall time substantially smaller than the input rise time. 9/30/2010 VLSI Design Lab,SVNIT
  • Ipeak as a Function of CL 2.5 x 10-4 When load capacitance is small, Ipeak is large. CL = 20 fF 2 1.5 CL = 100 fF 1 0.5 CL = 500 fF 0 0 2 4 -0.5 time (sec) 500 psec input slope 6 x 10-10 Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals slope engineering.
  • Psc as a Function of Rise/Fall Times 8 When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by Psc 7 VDD= 3.3 V 6 5 4 VDD = 2.5 V 3 2 1 VDD = 1.5V 0 0 2 tsin/tsou If VDD < VTn + |VTp| then Psc is eliminated since both devices are never on at the same time. 4 t W/Lp = 1.125 m/0.25 m W/Ln = 0.375 m/0.25 m CL = 30 fF normalized wrt zero input rise-time dissipation
  • Leakage (Static) Power Consumption VDD Ileakage Vout Drain junction leakage Gate leakage Sub-threshold current Sub-threshold current is the dominant factor. All increase exponentially with temperature! 9/30/2010 VLSI Design Lab,SVNIT
  • Leakage as a Function of VT  Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthreshold conduction a dominate component of power dissipation. 10-2 ID (A)  10-7 VT=0.4V VT=0.1V 10-12 0 0.2 0.4 0.6 VGS (V) 0.8 1 An 90mV/decade VT roll-off - so each 255mV increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance)
  • TSMC Processes Leakage and VT CL018 G CL018 LP CL018 ULP Vdd 1.8 V 1.8 V 1.8 V 2V 1.5 V 1.2 V Tox (effective) 42 Å 42 Å 42 Å 42 Å 29 Å 24 Å Lgate 0.16 m 0.16 m 0.18 m 0.13 m 0.11 m 0.08 m IDSat (n/p) (A/m) 600/260 500/180 320/130 780/360 860/370 920/400 20 1.60 0.15 300 1,800 13,000 0.42 V 0.63 V 0.73 V 0.40 V 0.29 V 0.25 V 30 22 14 43 52 80 Ioff (leakage) (A/m) VTn FET Perf. (GHz) CL018 HS CL015 HS CL013 HS From MPR, 2000
  • Exponential Increase in Leakage Currents 10000 Ileakage(nA/m) 1000 0.25 0.18 0.13 0.1 100 10 1 30 40 50 60 70 80 Temp(C) 90 100 110 From De,1999
  • Review: Energy & Power Equations E = CL VDD2 P01 + tsc VDD Ipeak P01 + VDD Ileakage f01 = P01 * fclock P = CL VDD2 f01 + tscVDD Ipeak f01 + VDD Ileakage Dynamic power (~90% today and decreasing relatively) 9/30/2010 Short-circuit power (~8% today and decreasing absolutely) VLSI Design Lab,SVNIT Leakage power (~2% today and increasing)
  • Power and Energy Design Space Constant Throughput/Latency Energy Design Time Variable Throughput/Latency Non-active Modules Logic Design Active Reduced Vdd Run Time DFS, DVS Clock Gating Sizing Multi-Vdd (Dynamic Freq, Voltage Scaling) Sleep Transistors Leakage + Multi-VT Multi-Vdd Variable VT 9/30/2010 VLSI Design Lab,SVNIT + Variable VT
  • Dynamic Power as a Function of Device Size • Device sizing affects dynamic energy consumption – gain is largest for networks with large overall effective fanouts (F = CL/Cg,1) The optimal gate sizing factor (f) for dynamic energy is smaller than the one for performance, especially for large F’s   e.g., for F=20, fopt(energy) = 3.53 while fopt(performance) = 4.47 If energy is a concern avoid oversizing beyond the optimal 1.5 F=1 normalized energy  F=2 1 F=5 0.5 F=10 F=20 0 9/30/2010 VLSI Design Lab,SVNIT 1 2 3 4 f 5 6 7
  • Dynamic Power Consumption is Data Dependent  Switching activity, P01, has two components   A static component – function of the logic topology A dynamic component – function of the timing behavior (glitching) Static transition probability P01 = Pout=0 x Pout=1 2-input NOR Gate A B 0 0 1 0 1 0 1 0 0 1 1 0 = P0 x (1-P0) Out 9/30/2010 With input signal probabilities PA=1 = 1/2 PB=1 = 1/2 NOR static transition probability = 3/4 x 1/4 = 3/16 VLSI Design Lab,SVNIT
  • NOR Gate Transition Probabilities  Switching activity is a strong function of the input signal statistics  PA and PB are the probabilities that inputs A and B are one A B 0 A B CL PA 1 0 PB P01 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB) 9/30/2010 VLSI Design Lab,SVNIT 1
  • Transition Probabilities for Some Basic Gates NOR OR NAND AND XOR P01 = Pout=0 x Pout=1 (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB) (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB)) PAPB x (1 - PAPB) (1 - PAPB) x PAPB (1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB) 0.5 A X 0.5 B Z For X: P01 = P0 x P1 = (1-PA) PA = 0.5 x 0.5 = 0.25 For Z: P01 = P0 x P1 = (1-PXPB) PXPB = (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16
  • Inter-signal Correlations • Determining switching activity is complicated by the fact that signals exhibit correlation in space and time – reconvergent fan-out (1-0.5)(1-0.5)x(1-(1-0.5)(1-0.5)) = 3/16 0.5 A 0.5 B X Z Reconvergent (1- 3/16 x 0.5) x (3/16 x 0.5) = 0.085 P(Z=1) = P(B=1) & P(A=1 | B=1)  Have to use conditional probabilities 9/30/2010 VLSI Design Lab,SVNIT
  • Logic Restructuring  Logic restructuring: changing the topology of a logic network to reduce transitions AND: P01 = P0 x P1 = (1 - PAPB) x PAPB 0.5 A B 0.5 (1-0.25)*0.25 = 3/16 W 7/64 X 15/256 C F D 0.5 0.5 0.5 A 0.5 B 3/16 Y 15/256 F 0.5 C 0.5 D Z 3/16 Chain implementation has a lower overall switching activity than the tree implementation for random inputs Ignores glitching effects 9/30/2010 VLSI Design Lab,SVNIT
  • Input Ordering (1-0.5x0.2)x(0.5x0.2)=0.09 0.5 A B 0.2 X C 0.1 F 0.2 B C 0.1 (1-0.2x0.1)x(0.2x0.1)=0.0196 X A 0.5 F Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5) 9/30/2010 VLSI Design Lab,SVNIT
  • Glitching in Static CMOS Networks  Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards)  glitch: node exhibits multiple transitions in a single cycle before settling to the correct logic value A B X Z C ABC 101 000 X Z 9/30/2010 Unit Delay VLSI Design Lab,SVNIT
  • Glitching in an RCA Cin S14 S15 S0 S1 S2 S Output Voltage (V) 3 S3 2 S4 Cin S2 S15 S5 1 S10 S1 S0 0 0 2 4 6 Time (ps) 8 10 12
  • What Causes Glitches? A A B X B X Z Y C Y C Z D D A,B A,B C,D C,D X X Y Y Z Z Uneven arrival times of input signals of gate due to unbalanced delay paths Solution: balancing delay paths! 9/30/2010 VLSI Design Lab,SVNIT
  • Power and Energy Design Space Constant Throughput/Latency Energy Design Time Variable Throughput/Latency Non-active Modules Logic Design Active Reduced Vdd Run Time DFS, DVS Clock Gating Sizing Multi-Vdd (Dynamic Freq, Voltage Scaling) Sleep Transistors Leakage + Multi-VT Multi-Vdd Variable VT 9/30/2010 VLSI Design Lab,SVNIT + Variable VT
  • Dynamic Power as a Function of VDD • Decreasing the VDD decreases dynamic energy consumption (quadratically) • But, increases gate delay (decreases performance) 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 VDD (V)  Determine the critical path(s) at design time and use high VDD for the transistors on those paths for speed. Use a lower VDD on the other gates, especially those that drive large capacitances (as this yields the largest energy benefits). 9/30/2010 VLSI Design Lab,SVNIT
  • Multiple VDD Considerations • How many VDD? – Two is becoming common – Many chips already have two supplies (one for core and one for I/O) • When combining multiple supplies, level converters are required whenever a module at the lower supply drives a gate at the higher supply (step-up) – If a gate supplied with VDDL drives a gate at VDDH, the PMOS never turns off V • The cross-coupled PMOS transistors do the level conversion • The NMOS transistor operate on a reduced supply Vin – Level converters are not needed for a step-down change in voltage 9/30/2010 VLSI Design Lab,SVNIT DDH VDDL Vout
  • Dual-Supply Inside a Logic Block • Minimum energy consumption is achieved if all logic paths are critical (have the same delay) • Clustered voltage-scaling – Each path starts with VDDH and switches to VDDL (gray logic gates) when delay slack is available – Level conversion is done in the flipflops at the end of the paths 9/30/2010 VLSI Design Lab,SVNIT
  • Power and Energy Design Space Constant Throughput/Latency Energy Design Time Variable Throughput/Latency Non-active Modules Logic Design Active Reduced Vdd Run Time DFS, DVS Clock Gating Sizing Multi-Vdd (Dynamic Freq, Voltage Scaling) Sleep Transistors Leakage + Multi-VT Multi-Vdd Variable VT 9/30/2010 VLSI Design Lab,SVNIT + Variable VT
  • Stack Effect • Leakage is a function of the circuit topology and the value of the inputs VT = VT0 + (|-2F + VSB| - |-2F|) where VT0 is the threshold voltage at VSB = 0; VSB is the source- bulk (substrate) voltage;  is the body-effect coefficient A A 0 0 1 1 B Out A VX B B 0 1 0 1 VX VT ln(1+n) 0 VDD-VT 0 ISUB VGS=VBS= -VX VGS=VBS=0 VGS=VBS= -Vx VSG=VSB=0  Leakage is least when A = B = 0  Leakage reduction due to stacked transistors is called the stack effect
  • Sub-threshold Leakage Off-current increases exponentially when reducing VTH 9/30/2010 VLSI Design Lab,SVNIT
  • • Reducing the VT increases the subthreshold leakage current (exponentially) – 90mV reduction in VT increases leakage by an order of magnitude ID (A) Sub threshold Leakage as a Function of Design Time VT • But, reducing VT decreases gate delay (increases performance) VT=0.4V VT=0.1V 0 0.2 0.4 0.6 0.8 1 VGS (V)  Determine the critical path(s) at design time and use low VT devices on the transistors on those paths for speed. Use a high VT on the other logic for leakage control.  A careful assignment of VT’s can reduce the leakage by as much as 80%
  • Dual-Thresholds Inside a Logic Block • Minimum energy consumption is achieved if all logic paths are critical (have the same delay) • Use lower threshold on timing-critical paths – Assignment can be done on a per gate or transistor basis; no clustering of the logic is needed – No level converters are needed 9/30/2010 VLSI Design Lab,SVNIT
  • Variable VT (ABB) at Run Time • VT = VT0 + (|-2F + VSB| - |-2F|)  For an n-channel device, the substrate is normally tied to ground (VSB = 0)  A negative bias on VSB causes VT to increase  Adjusting the substrate bias at run time is called adaptive body-biasing (ABB)  Requires process a dual well fab 0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4 -2.5 -2 -1.5 -1 VSB (V) -0.5 0
  • Transistors Leak • Drain leakage – Diffusion currents – Drain-induced barrier lowering (DIBL) • Junction leakages – Gate-induced drain leakage (GIDL) • Gate leakage – Tunneling currents through thin oxide 9/30/2010 VLSI Design Lab,SVNIT
  • Short Channel Factors and Stack Effect • In short-channel devices, the subthreshold leakage current depends on VGS,VBS and VDS. The VT of a short-channel device decreases with increasing VDS due to DIBL (draininduced barrier loading). 9/30/2010 VLSI Design Lab,SVNIT
  • Gate Tunneling V DD Exponential function of supply voltage • IGD~ e-ToxeVGD, IGS~ e-ToxeVGS • Independent of the sub-threshold leakage x 10 I SUB V DD 0V I GD -10 1.8 I Leak 90 nm CMOS 1.6 Igate (A) 1.4 I GS 1.2 1 Modeled in BSIM4 0.8 Also in BSIM3v3 (but not always included in foundry models) 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VDD (V) 0.7 0.8 0.9 1 NMOS gate leakage usually worse than PMOS
  • Other sources of static power dissipation • Diode (drain-substrate) reverse bias currents p+ n+ n+ p+ p+ n+ n well p substrate •Electron-hole pair generation in depletion region of reverse-biased diodes • Diffusion of minority carriers through junction • For sub-50nm technologies with highly-doped pn junctions, tunneling through narrow depletion region becomes an issue Strong function of temperature Much smaller than other leakage components in general
  • Other sources of static power dissipation • Circuit with dc bias currents: sense amplifiers, voltage converters and regulators, sensors, mixed-signal components, etc Should be turned off if not used, or standby current should be minimized 9/30/2010 VLSI Design Lab,SVNIT
  • Summary of Power Dissipation Sources P ~ a  CL  CCS Vswing VDD  f  I DC  I Leak VDD • • • • • a– switching activity CL – load capacitance CCS – short-circuit capacitance Vswing – voltage swing f – frequency   IDC – static current Ileak – leakage current energy P  rate  static power operation 9/30/2010 VLSI Design Lab,SVNIT
  • The Traditional Design Philosophy • Maximum performance is primary goal – Minimum delay at circuit level • Architecture implements the required function with target throughput, latency • Performance achieved through optimum sizing, logic mapping, architectural transformations. • Supplies, thresholds set to achieve maximum performance, subject to reliability constraints 9/30/2010 VLSI Design Lab,SVNIT