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Layouts and stick diag
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Layouts and stick diag

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  • 1. LAYOUTS
  • 2. NAND2 layout
  • 3. NOR2 layout
  • 4. 4 input NAND gate:( Not A preferrable layout)
  • 5. 8 input AND gate
  • 6. 2 I/P MUX AND ITS LAYOUTF’ = (A.S+B.S’)
  • 7. STICKDIAGRAMS
  • 8. CONCEPT• Popular Way Of symbolic design.• Free hand layout• Colored lines for various process layers.• Poly crossing diffusion gives transistors.• Metal touching diffusion gives contacts.
  • 9. Concept• Notation gives only relative position ofvarious design components.• A compactor is used to convert it intoabsolute design.• The compactor translates design rules intoconstraints on the component positions.• It also gives optimized design layout withefforts for minimization of area and costfunction.
  • 10. Pros and cons• Designer does not have to worry aboutdesign rules.• Compactor takes care of that.• Outcome of the compactor may beunpredictable and may not match manualapproach.
  • 11. Typical Stick Diagram
  • 12. Layers in the stick diagrams
  • 13. TheProcedureForDrawingStickDiagrams:
  • 14. Draw stick diagrams for the above circuits.
  • 15. Back end optimization of a circuitusingEulers Graph approach
  • 16. Constructing a minimum area layoutConstructing a minimum area layout
  • 17. Stick diagram layout of the complex CMOS logic gatewith arbitrary ordering of poly gate columns.
  • 18. Ordering of polysilicon gate columns in Euler graph sequence results inuninterrupted p-type and n-type diffusion areas.Adv: Compact area, simple routing of signals and less parasitic capacitance.
  • 19. Euler Graph Approach:(Good Density, Min Area, Abutting of S-D Connections,Single Diffusion Strip In Both Wells, , Easy Automation)Construction Of Logic Graph:1. Vertices : Nodes of the N/W.2. Edge: I/P.3. Dual Graphs for PUN & PDN.Identification Of Euler Paths:1. Path through all nodes such that an edge is visited only once.2. Uninterrupted diffusion strip in the layout is possible iff Eulerpath exists.3. Many solutions exist.4. Common Euler path in PUN & PDN5. Sequence of edges in the Euler path = Order of I/Ps in the layout.
  • 20. E - D - A - B - C
  • 21. Ex: 1.
  • 22. Ex: 2.
  • 23. Ex: 3.Effect Of Restructuring
  • 24. Ex: 3.Effect Of Restructuring
  • 25. Ex: 3.Effect Of Restructuring
  • 26. Sketch a stick diagram for a combinational circuit evaluating followingBoolean expression.

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