11                       EE 560               MOS TRANSISTOR THEORY                                               PART 2  ...
nMOS TRANSISTOR IN LINEAR REGION                                                                 2                 VS = 0 ...
3         nMOS TRANSISTOR IN SATURATION REGION                               VGS = VG > VT0          VDS = VD > VDSAT     ...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                        4  VS = VB = 0    VGS = VG > VT0          ...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                              5         VS = VB = 0    VGS G > VT0...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                        6 Boundary conditions:             Q I (y)...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                               7                     µ n C ox W                ID ...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                          8EXAMPLE 3.4For an n-MOS transistor with µn = 600 cm2/Vs...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                     9           VDS ≥ VGS - VT0 = VDSAT SATURATIO...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                10    CHANNEL LENGTH MODULATION                   ...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                          11                   VS = 0  VGS =VG > VT0 VDS =VD > VDS...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                   12                µ n C ox W                  µ...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                 13            SUBSTRATE BIAS EFFECT                              ...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                 14       n-MOS      D          p-MOS    S        ...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                            15 MEASUREMENT OF PARAMETERS (VT0, γ, ...
MOSFET CURRENT - VOLTAGE CHARACTERISTICS                                               16                                 ...
EFFECTIVE CHANNEL LENGTH AND WIDTH                   EFFECTIVE CHANNEL LENGTH AND WIDTH                                   ...
MOSFET - SCALING                               18 SCALING -> refers to ordered reduction in dimensions of the MOSFET and o...
MOSFET - SCALING                                        19     Alternative Scaling Rules: Constant Voltage Scaling, i.e. V...
Influence of Scaling on MOS Device Performance                20    PARAMETER                                             ...
21                                   MOSFET CAPACITANCES                                                             G    ...
MOSFET CAPACITANCES                   22                                         Cgb                                      ...
MOSFET CAPACITANCES                                23                                   ε       OXIDE Capacitances Cox = o...
MOSFET CAPACITANCES                         24           b. Gate - Channel                    MOSFET - Linear Region      ...
25    Capacitance                      Cut-off            Linear         Saturation      Cgb(total)                CoxWLef...
JUNCTION Capacitances -> Cdb, Csb                                                26                                       ...
JUNCTION Capacitances -> Cdb, Csb                                                       27                                ...
JUNCTION Capacitances -> Cdb, Csb                                                   28                                    ...
29                                                                     (F)          ε Si q  N A N D  1                  ...
30  n , p junctions (Sidewalls)     +     +                    εSi q  N A (sw) N D  1          Cj 0 s w=                ...
EXAMPLE 3-8                                                         31 Determine the total junction capacitance at the dra...
32where         ε Si q  N A N D  1  C j0 =           2  N A + N D  φ0                                       εSi q  ...
10 µm     G                      NA = 2 x 1015 cm-3                       33                                              ...
εSi q  N A (sw) N D  1                               34               =                  2  N A (sw) + N D  φ0sw     C...
35Area, Perimeter                                      Y=10µm                                                         2   ...
36                        Important 2nd Order Effects                          Short Channel Effects - Leff --> xj        ...
36Mobility Degradation due to Lateral Electric Field: VELOSITY SATURATION (very small channel lengths + high supply voltag...
37Short Channel Effect - Leff --> xj (source, drain diffusion depth)                    VT0 (short channel) = VT0 - ∆VT0∆L...
SPICE SIMUATION - MODELS                          38Level 1 (MOS1) - analylitical mode, ID(sat) is described by squarelaw ...
39SPICE MODELING OF MOS CAPACITANCESM1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U.                            ...
M1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P                              PS=11.5U PD=11.5U                 40..MODEL NFET NMOS...
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Ese570 mos theory_p206

  1. 1. 11 EE 560 MOS TRANSISTOR THEORY PART 2 GCA (gradual channel approximaton) MOS Tranistor Model Strong Inversion OperationKenneth R. Laker, University of Pennsylvania
  2. 2. nMOS TRANSISTOR IN LINEAR REGION 2 VS = 0 VGS = VG > VT0 VDS =VD = small ID channel SiO2 CGC CBC substrate depletion region or bulk B p nMOS TRANSISTOR AT EDGE OF SATURATION REGION VS = 0 VGS = VG > VT0 VDS =VD = VDSAT channel SiO2 CGC CBC substrate depletion region or bulk B p pinch-off pointKenneth R. Laker, University of Pennsylvania
  3. 3. 3 nMOS TRANSISTOR IN SATURATION REGION VGS = VG > VT0 VDS = VD > VDSAT VS = 0 VDS - VDSAT channel SIO2 VGD = VG - VD < VT0 CGC VCS(y) = VDSAT CBC y substrate x or bulk B p y=0 depletion region pinch-off pointKenneth R. Laker, University of Pennsylvania
  4. 4. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 4 VS = VB = 0 VGS = VG > VT0 ID VDS CGC CBC y substrate x or bulk B p y=0 y=Ly=0 y Channel length = L y=L Channel width = WSource Drain side side inversion layer (channel) dy Kenneth R. Laker, University of Pennsylvania
  5. 5. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 5 VS = VB = 0 VGS G > VT0 VT0 V = VG > ID VDS CGC CBC y substrate x or bulk B p y=0 y=L VCS(y) Assumptions:Boundary conditions: VT0(y) = VT0 VCS(y = 0) = VS = 0 VGS > VT0 VCS(y = L) = VDS VGD = VGS - VDS > VT0 Mobile charge in channel: Ey >> Ex Q I (y) = − Cox [VGS − VCS (y) − VT 0 ] (C/cm2) C Incremental R for differential channel segment C/s dy  1  µn = electron mobility dR = −   = cm2/Vsec W  µ n QI (y)  [µ −> U0 in SPICE]Kenneth R. Laker, University of Pennsylvania
  6. 6. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 6 Boundary conditions: Q I (y) = − Cox [VGS − VCS (y) − VT 0 ] VCS(y = 0) = VS = 0 dy  1  dR = −  VCS(y = L) = VDS W  µ n QI (y)   Voltage drop across ID incremental segment dy dVCS = I D dR = − dy W µ n Q I (y) Integrating along the channel 0 < y < L and 0 < VCS < VDS: L VDS ∫ I D dy = − W µ n ∫ Q I (y) dVCS 0 0 i.e. = W µ n C ox [(VGS − VT 0 ) VDS − VDS / 2] 2 µ n C ox W ID = [2(VGS − VT 0 ) VDS − VDS ] 2 2 LKenneth R. Laker, University of Pennsylvania
  7. 7. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 7 µ n C ox W ID = [2(VGS − VT 0 ) VDS − VDS ] 2 2 L k W k = µ n C ox = [2(VGS − VT 0 ) VDS − VDS ] 2 2 L [k -> KP in SPICE] k W = [2(VGS − VT 0 ) VDS − VDS ]2 k = k 2 LKenneth R. Laker, University of Pennsylvania
  8. 8. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 8EXAMPLE 3.4For an n-MOS transistor with µn = 600 cm2/Vsec, Cox = 7 x 10-8 F/cm2,W = 20 µm, L = 2 µm, VT0 = 1.0 V, plot the relationship between IDand VDS, VGS. k W I D = [2(VGS − VT 0 ) VDS − VDS ] where k = µ n C ox 2 2 L F = C/V W −8 2 20µ m k = µ n C ox = (600 cm /Vsec)(7 x10 F/cm ) 2 = 0.42 mA/V 2 L 2µ m I D = 0.21mA/V 2 [2(VGS − 1.0)V − VDS ] DS 2 LINEAR OR TRIODE REGION ID (mA) 4.0 V ≤ V − V VDS = VGS - VT0 DS GS T0 VGS = 5V Assumptions: 2.0 VGS = 4V VGS > VT0 VGD = VGS − VDS > VT0 VGS = 3V 0 VDS (V) 1.0 3.0 5.0 Kenneth R. Laker, University of Pennsylvania
  9. 9. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 9 VDS ≥ VGS - VT0 = VDSAT SATURATION REGION µ n C ox W ID = [2(VGS − VT 0 ) VDS − VDS ] @V = V 2 = VGS - VT0 2 L DS DSAT µ n C ox W = [2(VGS − VT 0 )(VGS − VT 0 ) − (VGS − VT 0 ) 2 ] 2 L µ n C ox W I D (sat) = (VGS − VT 0 )2 2 L VDS = VGS - VT0 ID(sat) ID (mA) 4.0 SAT LINEAR VGS = 5V 2.0 VGS = 4V VGS = 3V 0 VDS (V) 1.0 3.0 5.0Kenneth R. Laker, University of Pennsylvania VT0 VGS
  10. 10. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 10 CHANNEL LENGTH MODULATION Q I (y) = − Cox [VGS − VCS (y) − VT 0 ] Boundary conditions: VCS(y = 0) = VS = 0 Q I (y = 0) = − Cox [VGS − VT 0 ] VCS(y = L) = VDS Q1 (y = L) = − C ox [VGS − VDS − VT 0 ] = 0 @ VDS = VDSAT VS = 0 VGS =VG > VT0 VDS =VD > VDSAT CGC ∆L CBC L L substrate or bulk B p L = L − ∆L effective channel length VCS(y = L) = VDSATKenneth R. Laker, University of Pennsylvania
  11. 11. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 11 VS = 0 VGS =VG > VT0 VDS =VD > VDSAT CGC ∆L CBC L L substrate or bulk B p µ n C ox W µ C W I D (sat) = (VGS − VT 0 )2 = n ox (VGS − VT 0 )2 2 L 2 L(1 − ∆ L ) L where ∆ L ∝ VDS − VDSAT 1 emperical relation: ∆ L = 1 + λVDS [λ -> LAMBDA in SPICE] 1− L λ = channel length modulation coefficent (V-1)Kenneth R. Laker, University of Pennsylvania
  12. 12. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 12 µ n C ox W µ n C ox W I D (sat) = (VGS − VT 0 ) = 2 (VGS − VT 0 )2 2 L 2 L(1 − ∆ L ) 1 L ∆ L = 1 + λ VDS assume λVDS << 1 1− L µ n C ox W I D (sat) = (VGS − VT 0 )2 (1 + λ VDS ) LEVEL 1 2 L Model VDS = VGS - VT0 ID (mA) 4.0 λ≠0 VGS = 5V λ≠0 2.0 VGS = 4V λ≠0 VGS = 3V 0 VDS (V) 1.0 3.0 5.0Kenneth R. Laker, University of Pennsylvania
  13. 13. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 13 SUBSTRATE BIAS EFFECT LEVEL 1 Model (sat) ID = f(VGS, VDS, VSB)Kenneth R. Laker, University of Pennsylvania
  14. 14. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 14 n-MOS D p-MOS S + VDS - + ID VGS VSB - + -B G + -B G - VGS - + VSB ID S + VDS Dn-MOS I D = 0 for VGS ≤ VT VGS > VT, VDS < VGS - VT VGS > VT, VDS > VGS - VTp-MOS I D = 0 for VGS ≥ VT VGS < VT, VDS > VGS - VT VGS < VT, VDS < VGS - VT Kenneth R. Laker, University of Pennsylvania
  15. 15. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 15 MEASUREMENT OF PARAMETERS (VT0, γ, λ, kn, kp) W W k n = µ n Cox k p = µ p C ox L L D kn ID I D (sat) = (VGS − VT 0 )2 +V = VGS 2 G DS VGS B kn VSB I D (sat) = (VGS − VT 0 ) S + 2 VSB = 0 VSB > 0 ID Gamma VGSKenneth R. Laker, University of Pennsylvania VT0 VT1
  16. 16. MOSFET CURRENT - VOLTAGE CHARACTERISTICS 16 DC current meter Lambda D ID +VDS > VGS - VT0 G VGS = VT0 + 1 V + B S VBS = 0 ID VGS = VT0 + 1 I D (sat) = k n (VGS − VT 0 )2 (1+ λ VDS ) ID2 ID1 VGS = VT0 + 1 V I D 2 1 + λ VD S 2 VDS = VDS1 VDS2 I D1 1 + λ VD S 1Kenneth R. Laker, University of Pennsylvania
  17. 17. EFFECTIVE CHANNEL LENGTH AND WIDTH EFFECTIVE CHANNEL LENGTH AND WIDTH 17 G B S D CGC CGC n+ n+ CC n+ n+ BC BC L substrate orp bulk B p LD LD Leff LM SPICE Parameters Leff = LM - 2LD - DL LD -> under diffusion DL -> error in photolith and etch Weff = WM - DW SPICE ParametersKenneth R. Laker, University of Pennsylvania DW -> error in photolith and etch
  18. 18. MOSFET - SCALING 18 SCALING -> refers to ordered reduction in dimensions of the MOSFET and other VLSI features • Reduce Size of VLSI chips. • Change operational charateristics of MOSFETs and parasitics. • Phyiscal limits restrict degree of scaling that can be achieved. SCALING FACTOR = α > 1 --> S First-order "constant field" MOS scaling theory: The electric field E is kept constant, and the scaled device is obtained by applying a dimensionless scale-factor α to reduce dimensions by (1/α) and maintain E unchanged: a. All dimensions, including those vertical to the surface (1/α) b. device voltages (1/α) c. the concentration densities (α). (1/α)/(1/α) = 1 α(1/α) = 1 <=>Kenneth R. Laker, University of Pennsylvania
  19. 19. MOSFET - SCALING 19 Alternative Scaling Rules: Constant Voltage Scaling, i.e. VDD is kept constant, while the process dimensions are scaled by (1/α). a. All dimensions, including those vertical to the surface (1/α) b. device voltages (1) c. the concentration densities (α2) to preserve charge-field relations. 1/(1/α) = α α2(1/α) = α <=> Lateral Scaling: only the gate length is scaled L = 1/α (gate-shrink). Year 1991 1993 1995 1997 1999 2001 2003 2005 Feature Size(µm) 1.00 0.80 0.60 0.35 0.25 0.18 0.13 0.09 Historical reduction in min feature size for typical CMOS ProcessKenneth R. Laker, University of Pennsylvania
  20. 20. Influence of Scaling on MOS Device Performance 20 PARAMETER SCALING MODEL Constant Field Constant Voltage Lateral Length (L) 1/α 1/α 1/α Width (W) 1/α 1/α 1 Supply Voltage (V) 1/α 1 1 Gate Oxide thickness (tox) 1/α 1/α 1 Junction depth (Xj) 1/α 1/α 1 Substrate Doping (NA) α α2 1 Current (I) - (W/L) (1/tox)V2 1/α α α Power Dissipation (P) - IV 1/α2 α α Power Density (P/Area) 1 **(α3)** α2 Electric Field Across Gate Oxide - V/tox 1 α 1 Load Capacitance (C) - WL (1/tox) 1/α 1/α 1/α Gate Delay (T) - VC/I 1/α 1/α2 1/α2Kenneth R. Laker, University of Pennsylvania
  21. 21. 21 MOSFET CAPACITANCES G B S D CGC CGC p n+ n+ CBC CBC n+ n+ substrate p or bulk B LD LD Leff LM Y substrate or bulk B LD LD n+ n+ pKenneth R. Laker, University of Pennsylvania
  22. 22. MOSFET CAPACITANCES 22 Cgb D Cgd Cdb MOSFET G (DC MODEL) B Cgs Csb S Cgd, Cgs, Cgb -> Oxide Capacitances Cdb, Csb -> Junction CapacitancesKenneth R. Laker, University of Pennsylvania
  23. 23. MOSFET CAPACITANCES 23 ε OXIDE Capacitances Cox = ox t ox a. Overlap Caps CGS0(overlap) = Cox W LD ALL MOSFET OPERATION CGD0(overlap) = Cox W LD REGIONS CGB0(overlap) = Cox WovLeff L = LD in SPICE D SPICE: CoxLD = CGS0; CoxLD = CGD0; CoxWov = CGB0 b. Gate - Channel Cgb, Cgb and Cgb MOSFET - Cut-off Region Cgb = Cox W Leff Cgs = Cgd = 0 (no conducting channel in cut-off) pKenneth R. Laker, University of Pennsylvania
  24. 24. MOSFET CAPACITANCES 24 b. Gate - Channel MOSFET - Linear Region Cgb = 0 Cgs = (1/2) Cox W Leff p Cgd = (1/2) Cox W Leff Cgb = 0 Cgs = (2/3) Cox W Leff p Cgd = 0Kenneth R. Laker, University of Pennsylvania
  25. 25. 25 Capacitance Cut-off Linear Saturation Cgb(total) CoxWLeff 0 + CGB0 0 + CGB0 + CGB0 0.5CoxWLeff + 0 + C Cgd(total) 0 + CGD0 CGD0 GD0 0 +CGS0 0.5CoxWLeff + (2/3)Cox WLeff Cgs(total) CGS0 + CGS0 Gate -to Channel/Bulk Cap Contribution(C/CoxWL) Cut-off Saturation Linear 1 Cgb Cgs 2/3 1/2 CgdCGD0 = CGS0 CGB0 VGS VT VT + VDS Kenneth R. Laker, University of Pennsylvania
  26. 26. JUNCTION Capacitances -> Cdb, Csb 26 xj p xd Y 2 xj 1 5 3 W n+ Channel n+ 4 Source DrainKenneth R. Laker, University of Pennsylvania
  27. 27. JUNCTION Capacitances -> Cdb, Csb 27 Y 2 xj 1 5 3 W n+ Channel n+ 4 [xj -> XJ in SPICE] Source Drain Junction Area Type 1 W xj n+/p p - Substrate -> NA 2 Y xj n+/p+ p+ - Channel-stop -> 10NA 3 W xj n+/p+ 4 Y xj n+/p+ 5 WY n+/pKenneth R. Laker, University of Pennsylvania
  28. 28. JUNCTION Capacitances -> Cdb, Csb 28 ND xjn+, p junctions xd p N A 2ε Si  1 1  V = Ext bias --> VBD , VBSxd = + (φ0 − V) q  NA ND    kT  N A N D  built-in junction φ0 = q  n 2  potential ln  i  [φ0 -> PB in SPICE] Depletion-region charge  N AN D   N AN D  A = junction Q j = Aq  x d = A 2ε Si q  N + N  (φ0 − V) area  NA + N D   A D [AS, AD -> Source, Drain Areas in SPICE]Kenneth R. Laker, University of Pennsylvania
  29. 29. 29 (F) ε Si q  N A N D  1 m = grading coefficent C j0 =  N + N  φ (F/cm2) m = 1/2 for abrupt junction 2  A D 0 [m = MJ in SPICE] Cj(V) = Cj0 when V = 0 [Cj0 -> CJ in SPICE] [φ0 -> PB in SPICE]EQUIVALENT LARGE SIGNAL CAPACTIANCE 0 < Keq < 1 --> Voltage Equiv FactorKenneth R. Laker, University of Pennsylvania
  30. 30. 30 n , p junctions (Sidewalls) + + εSi q  N A (sw) N D  1 Cj 0 s w= (F/cm2) 2  N A (sw) + ND  φ0 s w   Since all sidewalls have depth = xj: [xj -> XJ in SPICE] Cjsw = Cj0sw xj (F/cm) [Cjsw -> CJSW in SPICE]EQUIVALENT LARGE SIGNAL CAPACTIANCE P = sidewall perimeter [PS, PD -> Source, Drain Perimeters in SPICE] 2φ0 s w  V2  1 /2  V1   1 /2 K eq (sw) = − 1 −  − 1 − φ   m(sw) = 1/2 (V2 − V1 )  φ0 s w   0 s w   [m(sw) -> MJSW in SPICE]Kenneth R. Laker, University of Pennsylvania
  31. 31. EXAMPLE 3-8 31 Determine the total junction capacitance at the drain, i.e. Cdb, for the n-channel enhancement MOSFET in Fig. 1. The process parameters are Substrate doping NA = 2 x 1015 cm-3 Source/drain (n+) doping ND = 1020 cm-3 Sidewall (p+) doping NA(sw) = 4 x 1016 cm-3 Gate oxide thickness tox = 45 nm Junction depth xj = 1.0 µm 10 µm G 5 µm D S n+ n+ Figure 1 2 µm Source, Drain are surrounded by p+ channel-stop. The substrate is biased at 0V. Assume the drain voltage range is 0.5 V to 5.0 V.Kenneth R. Laker, University of Pennsylvania
  32. 32. 32where ε Si q  N A N D  1 C j0 = 2  N A + N D  φ0   εSi q  N A (sw) N D  1 Cj 0 s w= 2  N A (sw) + ND  φ0 s w  
  33. 33. 10 µm G NA = 2 x 1015 cm-3 33 ND = 1020 cm-3 5 µm D S NA(sw) = 4 x 1016 cm-3 n+ n+ tox = 45 nm xj = 1.0 µm Figure 1 2 µmφ0, φ0sw kT  N A N D   (2 x10 15 )10 20 φ0 = ln   = 0.026 Vln 2.1x10 20  = 0.896 V q  ni 2   kT  N A (sw)N D   (4 x1016 )10 20 φ0 s w = ln  = 0.026 Vln  2.1x1020  = 0.975V q  ni2   Cj0, Cj0sw ε Si q  N A N D  1 C j0 = 2  N A + N D  φ0   F = C/V (1.04 x10 −12 F/cm)(1.6 x10 −19 C)  (2 x10 15 )10 20  1 =  2  2 x10 15 + 10 20  0.896V  = 1.35 x10 −8 F/cm 2 Kenneth R. Laker, University of Pennsylvania
  34. 34. εSi q  N A (sw) N D  1 34 = 2  N A (sw) + N D  φ0sw C j0 sw   (1.04 x10 −12 F/cm)(1.6 x10 −19 C)  (4 x10 16 )10 20  1 =   2  4 x10 16 + 10 20  0.975V −8 = 5.83x10 F/cm 2 Cjsw and xj = 1.0 µm = 10-4 cm Cjsw = Cj0sw xj = (5.83x10 F/cm2 )(10 −4 cm) = 5.83pF/cm −8 Keq, Keq(sw) VBD1 = VB - VD1 = 0 - 0.5V = -0.5V VBD2 = VB - VD2 = 0 - 5V = -5VKenneth R. Laker, University of Pennsylvania
  35. 35. 35Area, Perimeter Y=10µm 2 xj = 1µm 1 5 3 W = 5 µm n + Channel PD n+ 4Source Drain 10 µm G AD: n+/p junctions: S 5 µm D AD = (5 x 1) µm2 + (10 x 5) µm2 n+ n+ = 55 µm2 PD: n+/p+ junctions: Figure 1 2 µm PD = 2Y + W = 20 µm + 5 µm = 25 µmKenneth R. Laker, University of Pennsylvania
  36. 36. 36 Important 2nd Order Effects Short Channel Effects - Leff --> xj Narrow Channel Effects - W --> xdm Subthreshold Current - VGS < VT0Kenneth R. Laker, University of Pennsylvania
  37. 37. 36Mobility Degradation due to Lateral Electric Field: VELOSITY SATURATION (very small channel lengths + high supply voltages) velosity(vD) vDsat slope µs Note µs < µ0 µ = v /E Ey 0 sat crit slope = µ0 E Ecrit [SPICE Parameters: U0 -> µ0, UCRIT -> Ecrit, VMAX -> vsat] ID(sat) = W vDSAT Cox (VGS - VT) Note: ID(sat) = linear f(VGS - VT), independent of LMobility Degradation due to Normal Electric Field: (due to gate voltage across very thin oxide-depletion layer) Ex [SPICE Parameter: THETA -> θ] θ = imperical mobility modulation factorKenneth R. Laker, University of Pennsylvania
  38. 38. 37Short Channel Effect - Leff --> xj (source, drain diffusion depth) VT0 (short channel) = VT0 - ∆VT0∆LS, ∆LD = lateral extensions at source, drain of depletionregion due to reverse biased sourse, drain junctions withsubstrateNarrow Channel Effect - W --> xdm (depletion region depth) VT0 (narrow channel) = VT0 + ∆VT0 [SPICE Parameter: DELTA -> δ = imperical channel width factor] Subthreshold Current - VGS < VT0 (Spice Model) Ion = ID in strong inversion and VGS = Von is the boundary weak and strong inversionKenneth R. Laker, University of Pennsylvania
  39. 39. SPICE SIMUATION - MODELS 38Level 1 (MOS1) - analylitical mode, ID(sat) is described by squarelaw - strong inversion (with Channel Length Modulation). Basedon GCA (gradual channel approximaton) equations in Ch3.Level 2 (MOS2) - anaylitical model, more detailed than MOS1.Includes second order effects, e.g. mobility degradation, smallchannel effects and sub-threshold currents. Relaxes somesimplifying GCA assumptions.Level 3 (MOS3) - semi-emperical model. Uses simplerexpressions than MOS2 plus emperical equations to fitexperimental data. Improves accuracy and reduces simulationtime.BSIM3 (Berkeley Short-Channel IGFET Model) - includessub-micron MOSFET characteristics. Analytically simple, makesfull use of parameters extracted from experimental data.Kenneth R. Laker, University of Pennsylvania
  40. 40. 39SPICE MODELING OF MOS CAPACITANCESM1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U. m m2. m. U = 10-6.MODEL NFET NMOS m F/m+ TOX=200E-10 P = 10-12+ CGBO=200P CGSO=300P CGDO=300P+ CJ=200U CJSW=400P MJ=0.5 MJSW=0.3 PB=0.7 V F/m2 F/mM1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U D G S B Cgb = W × L × Cox = (4E-6 m) × (1E-6 m) × (17E-3 F/m2) = 6.8 fF Kenneth R. Laker, University of Pennsylvania
  41. 41. M1 4 3 5 0 NFET W=4U L=1U AS=15P AD=15P PS=11.5U PD=11.5U 40..MODEL NFET NMOS+ TOX=200E-8+ CGBO=200P CGSO=300P CGDO=300P+ CJ=200U CJSW=400P MJ=0.5 MJSW=0.3 PB=0.7 CJ = zero-bias junction capacitance per junction area (200 × 10-6 F/m2 = 2 × 10-4 pF/µm2) CJSW = zero-bias junction capacitance per junction periphery (400 × 10-12 F/m = 4 × 10-10 pF/µm) MJ = grading coefficient of junction bottom (0.5) MJSW = grading coefficient of junction side-wall (0.3) VJ = the junction potential (Vsb, Vdb for n-channel, Vbs, Vbd for p-channel) PB = the built-in voltage (+0.7 V) Area = AS or AD, the area of source or drain (15 × 10-12 m2 = 15 µm2) Periphery = PS or PD, the periphery of source or drain (11.5 × 10-6 m = 11.5 µm) Kenneth R. Laker, University of Pennsylvania
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