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Digital VLSI Design & FPGA Implementation

Prepared by :
AMBER BHAUMIK
About The Training
Objective
The Program emphasizes on imparting overall exposure to the concept and design methodologies ...
WHAT IS VLSI ?
VLSI is the short-form for Very-large-scale integration, a process that means to create
integrated circuits...
What is an FPGA?
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer...
Introduction to VLSI, IC History, EDA Tools

Module -I ( 1st Week)

About VLSI
VLSI is the field which involves packing mo...
Introduction to VLSI, IC History, EDA Tools

Module -I ( 1st Week)

Integration Level Trends
The figure shows that every 2...
Basics of Digital Design

Module -I ( 1st Week)

From transistors to chips
Chips from the bottom up:
1) Basic building blo...
Basics of Digital Design
Six types of gates
NOT , AND , OR, XOR, NAND, NOR
NOT Gate
A NOT gate accepts one input signal (0...
Basics of Digital Design

Module -I ( 1st Week)

XOR Gate
An XOR gate accepts two input signals If both are the same, the ...
Basics of Digital Design
Combinational circuit
The input values explicitly determine the output.
Gates are combined into c...
Basics of Digital Design

Module -I ( 1st Week)

Properties of Boolean Algebra

Adders
At the digital logic level, additio...
Basics of Digital Design
Full adder
A circuit that takes the carry-in value into account

Basic Laws of Boolean Algebra
Id...
Basics of Digital Design

Module -I ( 1st Week)

Sequential circuit
The output is a function of the input values and the e...
Introduction to VHDL : Target device is from Xilinx & Spartan 3
INTRODUCTION TO VHDL
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
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
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



Need, Scope, Use a...
Need, Scope, Use and History of VHDL

Module -II (2nd Week)

VHDL is a language for describing digital electronic systems....
Need, Scope, Use and History of VHDL(cont)

Module -II (2nd Week)

Uses and Benefits
 Fits effectively into
– structured,...
Need, Scope, Use and History of VHDL(cont)

Module -II (2nd Week)

History
The Requirement
The development of VHDL was ini...
VLSI Design(FPGA) process
Example: Design and implement a simple unit permitting to
speed up encryption with RC5-similar c...
Design Simulation and Design Synthesis

Module -II (2nd Week)

Synthesis
Is the process of translating a design descriptio...
VHDL Modelling Styles

Module -II (2nd Week)

There are three modeling styles:
 Behavioral
 Data flow
 Structural
Behav...
VHDL Modelling Styles

Module -II (2nd Week)

Dataflow

Structural

In the data flow approach, circuits are described by
i...
Data Types in VHDL

Module -II (2nd Week)

VHDL provides a number of basic, or scalar, types, and a means of forming compo...
Data Types in VHDL

Module -II (2nd Week)

3) Enumeration
An enumeration type is an ordered set of identifiers or characte...
Data Types in VHDL

Module -II (2nd Week)

Composite types
1) Arrays
An array in VHDL is an indexed collection of elements...
Objects in VHDL

Module -II (2nd Week)

An object is a named item in a VHDL description which has a value of a specified t...
Objects & Operators in VHDL

Module -II (2nd Week)

3) Signals
It is used for communication between VHDL components .Real,...
Operators in VHDL

Module -II (2nd Week)

3) Sign operators
The sign operators (+ and –) and the addition (+) and subtract...
Operators in VHDL
5)

Misc. Operators
These are as follows
** exponentiation
left operand = integer or floating point
righ...
CONDITIONAL STATEMENTS AND LOOPS IN VHDL

Module -II (2nd Week)

With Select Statements
A selected assignment statement is...
CONDITIONAL STATEMENTS AND LOOPS IN VHDL

Module -II (2nd Week)

When Else Statements
When is one of the fundamental concu...
CONDITIONAL STATEMENTS AND LOOPS IN VHDL

Module -II (2nd Week)

If Statement
Conditional structure. The if statement in V...
CONDITIONAL STATEMENTS AND LOOPS IN VHDL

Module -II (2nd Week)

Case Statements
Execute one specific case of an expressio...
CONDITIONAL STATEMENTS AND LOOPS IN VHDL

Module -II (2nd Week)

Loop Statements
VHDL has a basic loop statement, which ca...
STRUCTURAL STYLE

Module -III (3rd Week)

Structural Style of Modelling
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Structural VHDL describes the arr...
STRUCTURAL STYLE

Module -III (3rd Week)

Component declaration
Before components can be instantiated they need to be decl...
STRUCTURAL STYLE

Module -III (3rd Week)

Component Instantiation and interconnections
The component instantiation stateme...
COUNTERS

Module -III (3rd Week)

Counters
A counter is a device which stores (and sometimes displays) the number of times...
COUNTERS

Module -III (3rd Week)

The disadvantage to this counter is that it must be preloaded with the desired pattern (...
COUNTERS

Module -III (3rd Week)

BCD Counter
A 4-bit BCD-counter built with JK-flip flops. This is an asynchronous implem...
Flip Flops & Latches

Module -III (3rd Week)

 A flip-flop or latch is a circuit that has two stable states and can be us...
Flip Flops

Module -III (3rd Week)

R-S FLIP-FLOP
When using static gates as building blocks, the most fundamental latch i...
Flip Flops

Module -III (3rd Week)

JK flip-flop
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Rese...
Flip Flops

Module -III (3rd Week)

D flip-flop
The D flip-flop is the most common flip-flop in use today. It is better know...
Shift Registers

Module -IV (4th Week)

A register is a digital circuit with two basic functions: Data Storage and Data Mo...
Shift Registers
Shift Register Characteristics
Types
 Serial-in, Serial-out
 Serial-in, Parallel-out
 Parallel-in, Seri...
Shift Registers

Module -IV (4th Week)

Serial-In Serial-Out
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Data bits come in one at a time and leave one at a t...
Shift Registers
Serial-to-Parallel Conversion
We often need to convert from serial to parallel
e.g., after receiving a ser...
Shift Registers

Module -IV (4th Week)

Parallel-to-Serial Conversion
We use a Parallel-in Serial-out Shift Register.
The ...
Shift Registers

Module -IV (4th Week)

Parallel in parallel out
All data bits appear on the parallel outputs immediately ...
Finite State Machines

Module -IV (4th Week)

A finite state machine a set of states and two functions called the next sta...
Finite State Machines

Module -IV (4th Week)

Finite state machine design procedure
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Deriving state diagram
Deri...
Finite State Machines

Module -IV (4th Week)

Example:
FSM design procedure: state diagram to encode state transition tabl...
Finite State Machines
Implementation
D flip-flop for each state bit
Combinational logic based on encoding

Module -IV (4th...
Mini Projects Based on FPGA

Module -V (5th & 6th Week)

Each student after completing 4 modules have to start industry st...
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Transcript of "Digital VLSI Design and FPGA Implementation"

  1. 1. Digital VLSI Design & FPGA Implementation Prepared by : AMBER BHAUMIK
  2. 2. About The Training Objective The Program emphasizes on imparting overall exposure to the concept and design methodologies of all major aspects of VLSI engineering relevant to the industry's needs. Program offers in-depth hands-on training on various design methodologies used in industries. The course is comprehensive and rigorous, enabling the student to quickly ramp up to the level of real-world project readiness thus enhancing his/ her career prospects in the industry. Training Contents          VLSI Fundamentals & Digital Design Introduction to VHDL Overview of HDL-Based Design Getting Started Design Description Design Entry Synthesizing the Design Behavioral Simulation FPGA Implementation Lab Work The Labs for this training provides a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, simulated and implemented by the student. Student will simulate some good applications. After Completing this training: Student will be ready to design any digital design using VHDL.
  3. 3. WHAT IS VLSI ? VLSI is the short-form for Very-large-scale integration, a process that means to create integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI finds immediate application in DSP, Communications, Microwave and RF, MEMS, Cryptography, Consumer Electronics, Automobiles, Space Applications, Robotics, and Health industry. Nearly all modern chips employ VLSI architectures, or ULSI (ultra large scale integration). The line that demarcates VLSI from ULSI is very thin. SCOPE OF VLSI There is a rising demand for chip driven products in consumer electronics, medical electronics, communication, aero-space, computers etc. More and more chip designing companies have set up their units in India eying on the Indian talents; besides many of the Indian Major IT companies have forayed in Application Specific Integrated Circuit (ASIC) design in a big way. With the design & manufacturing market (both domestic & international) expanding rapidly, there is an enhanced demand of trained professionals who will boost the technical work force in the VLSI domain.
  4. 4. What is an FPGA? A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), FPGAs can be used to implement any logical function that an ASIC could perform. The FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic cells that can be viewed as standard components. Each logic cell can independently take on any one of a limited set of personalities. The individual cells are interconnected by a matrix of Block RAMs Block RAMs wires and programmable switches. A user's design is implemented by specifying the simple logic function for each cell and selectively closing the switches in the interconnect matrix. The array of logic cells and interconnect form a fabric of basic building blocks for logic circuits. Complex designs are created by combining these basic blocks to create the desired circuit. Implementation includes many phases Configurable Logic Blocks I/O Blocks Block RAMs  Translate : Merge multiple design files into a single netlist  Map : Group Logical symbols from the netlist (Gates) into physical components (CLB s and IOBs )  Place & Route : Place components onto the chip, connect them and extracts timing data into reports  Timing (Sim) : Generate a back annotated netlist for timing simulation tools  Configure : Generate a bit stream for device configuration
  5. 5. Introduction to VLSI, IC History, EDA Tools Module -I ( 1st Week) About VLSI VLSI is the field which involves packing more and more logic devices into smaller and smaller areas. Thanks to VLSI, circuits that would have taken boardfuls of space can now be put into a small space few millimetres across! This has opened up a big opportunity to do things that were not possible before. VLSI circuits are everywhere ... your computer, your car, your brand new state-of-the-art digital camera, the cell-phones, and what have you. All this involves a lot of expertise on many fronts within the same field, which we will look at in later sections. Integrated Circuits (Chips) Integrated circuits consist of: -- A small square or rectangular “die”, < 1mm thick  Small die: 1.5 mm x 1.5 mm => 2.25 mm2  Large die: 15 mm x 15 mm => 225 mm2 -- Larger die sizes mean:  More logic, memory  Less volume  Less yield -- Dies are made from silicon (substrate)  Substrate provides mechanical support and electrical common point IC History in terms of number of Transistors  SSI – Small-Scale Integration (0-102)  MSI – Medium-Scale Integration (102-103)  LSI – Large-Scale Integration (103-105)  VLSI – Very Large-Scale Integration (105-107)  ULSI – Ultra Large-Scale Integration (>=107)
  6. 6. Introduction to VLSI, IC History, EDA Tools Module -I ( 1st Week) Integration Level Trends The figure shows that every 2 years the number of components on an area of silicon(chip) doubled, which is called Moore’s Law. Obligatory historical Moore’s law plot Electronic design automation (EDA)- Set of software tools used for VLSI chip design. EDA Tool Categories: 2. Bases on Design Flows 1. Based on design methodology     Full Custom Design Standard Cell Based Design FPGA Design Structured ASIC Design  Implementation Tools  Logic and Physical Synthesis  Full Custom Layout  Floor Planning  Place & Route  Verification Tools  Simulation  Timing Analysis  Formal verification  Power analysis  Signal integrity  DRC and LVS
  7. 7. Basics of Digital Design Module -I ( 1st Week) From transistors to chips Chips from the bottom up: 1) Basic building block: the transistor = “on/off switch” 2) Digital signals – voltage levels high/low 3) Transistors are used to build logic gates 4) Logic gates make up functional and control units 5) Microprocessors contain several functional and control units This section provides an introduction into digital logic 1) Combinatorial and sequential logic 2) Boolean algebra and truth tables. 3) Basic logic circuits. 4) Decoders, multiplexers, latches, flip-flops. 5) Simple register design. Boolean expressions Uses Boolean algebra, a mathematical notation for expressing two-valued logic Logic diagrams A graphical representation of a circuit; each gate has its own symbol. Logic blocks are categorized as one of two types, depending on whether they contain memory. Blocks without memory are called combinational; the output of a combinational block depends only on the current input. In blocks with memory, the outputs can depend on both the inputs and the value stored in memory, which is called the state of the logic block. Truth tables A table showing all possible input value and the associated output values. Truth tables can completely describe any combinational logic function; how- ever, they grow in size quickly and may not be easy to understand. Sometimes we want to construct a logic function that will be 0 for many input combinations, and we use a shorthand of specifying only the truth table entries for the nonzero out- puts.
  8. 8. Basics of Digital Design Six types of gates NOT , AND , OR, XOR, NAND, NOR NOT Gate A NOT gate accepts one input signal (0 or 1) and returns the opposite signal as output AND Gate An AND gate accepts two input signals If both are 1, the output is 1; otherwise, the output is 0 OR Gate An OR gate accepts two input signals. If both are 0, the output is 0; otherwise, the output is 1 Module -I ( 1st Week)
  9. 9. Basics of Digital Design Module -I ( 1st Week) XOR Gate An XOR gate accepts two input signals If both are the same, the output is 0; otherwise, the output is 1 The difference between the XOR gate and the OR gate; they differ only in one input situation. When both input signals are 1, the OR gate produces a 1 and the XOR produces a 0. XOR is called the exclusive OR. NAND Gate The NAND gate accepts two input signals, If both are 1, the output is 0; otherwise, the output is 1 NOR Gate The NOR gate accepts two input signals If both are 0, the output is 1; otherwise, the output is 0
  10. 10. Basics of Digital Design Combinational circuit The input values explicitly determine the output. Gates are combined into circuits by using the output of one gate as the input for another. Three inputs require eight rows to describe all possible input combinations. This same circuit using a Boolean expression is (AB + AC). Circuit equivalence Two circuits that produce the same output for identical input. Boolean algebra allows us to apply provable mathematical principles to help design circuits. A(B + C) = AB + BC (distributive law) so circuits must be equivalent. Module -I ( 1st Week)
  11. 11. Basics of Digital Design Module -I ( 1st Week) Properties of Boolean Algebra Adders At the digital logic level, addition is performed in binary Addition operations are carried out by special circuits called, appropriately, adders. The result of adding two binary digits could produce a carry value Recall that 1 + 1 = 10 in base two . Half adder A circuit that computes the sum of two bits and produces the correct carry bit Boolean expressions sum = A B carry = AB
  12. 12. Basics of Digital Design Full adder A circuit that takes the carry-in value into account Basic Laws of Boolean Algebra Identity laws: A + 0 = A A*1=A Inverse laws: A + A = 1 A*A=0 Zero and one laws: A + 1 = 1 A*0=0 Commutative laws: A + B = B+A A*B=B*A Associative laws: A + (B + C) = (A + B) + C A * (B * C) = (A * B) * C Distributive laws : A * (B + C) = (A * B) + (A * C) A + (B * C) = (A + B) * (A + C) Module -I ( 1st Week)
  13. 13. Basics of Digital Design Module -I ( 1st Week) Sequential circuit The output is a function of the input values and the existing state of the circuit We describe the circuit operations using Boolean expressions Logic diagrams Truth tables Circuits as Memory Digital circuits can be used to store information These circuits form a sequential circuit, because the output of the circuit is also used as input to the circuit Example An S-R latch stores a single binary digit (1 or 0).There are several ways an S-R latch circuit can be designed using various kinds of gates. The design of this circuit guarantees that the two outputs X and Y are always complements of each other. The value of X at any point in time is considered to be the current state of the circuit. Therefore, if X is 1, the circuit is storing a 1; if X is 0, the circuit is storing a 0
  14. 14. Introduction to VHDL : Target device is from Xilinx & Spartan 3 INTRODUCTION TO VHDL          Need, Scope, Use and History of VHDL Application of VHDL in Market and Industries Special Features of this Language Design Process and Steps Design Simulation and Design Synthesis Design Methodology VHDL Modelling Styles Discussion on VHDL and Other Languages Data Types, Objects & Operators in VHDL CONDITIONAL STATEMENTS AND LOOPS IN VHDL      With Select Statements When Else Statements If Statement Case Statement Loops in VHDL STRUCTURAL STYLE  Components  Benefits of Structural Style  Structural Style of Modelling FLIP FLOPS, COUNTERS  Up/Down Binary & BCD Counters  1D and 2D Array in VHDL  Flip Flops and Latches  Shift Registers STATE MACHINES  Moore's Machine  Traffic Light Controller FPGA HARDWARE INTERFACING Module -II (2nd Week)
  15. 15. Need, Scope, Use and History of VHDL Module -II (2nd Week) VHDL is a language for describing digital electronic systems. It arose out of the United States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. VHSIC Hardware Description Language (VHDL) was developed, and subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE) in the US. Need VHDL is designed to fill a number of needs in the design process. 1) It allows description of the structure of a design, that is how it is decomposed into sub-designs, and how those sub designs are interconnected. 2) It allows the specification of the function of designs using familiar programming language forms. 3) As a result, it allows a design to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping. Scope VHDL is suited to the specification, design and description of digital electronic hardware. System level VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-software split. Simulation at this level is usually stochastic, and is concerned with modeling performance, throughput, queuing and statistical distributions. VHDL has been used in this area with some success, but is best suited to functional and not stochastic simulation. Digital VHDL is suitable for use today in the digital hardware design process, from specification through high-level functional simulation, manual design and logic synthesis down to gate-level simulation. VHDL tools usually provide an integrated design environment in this area.VHDL is not suited for specialized implementation-level design verification tools such as analog simulation, switch level simulation and worst case timing simulation. VHDL can be used to simulate gate level fan-out loading effects providing coding styles are adhered to and delay calculation tools are available.
  16. 16. Need, Scope, Use and History of VHDL(cont) Module -II (2nd Week) Uses and Benefits  Fits effectively into – structured, top down electronic design process – hierarchical design database structure – mixed design database, i.e., circuit schematic, IP & VHDL.  VHDL programming language includes concurrent language constructs ideally suited to hardware description  The use of VHDL is not restricted to electronics, though non electronic applications are unlikely.  Reduces Time To Market (TTM).  Enables implementation of increased complexity designs  Provides higher quality designs  Provides common, language-based description of digital hardware operation  Guidelines on writing VHDL models for synthesis commonly exist within design group  Effective design documentation : Provides a detailed specification which can be executed.  Simpler maintenance than schematic-based capture methods for well commented VHDL code  Enables exploration of alternative system architectures early in design cycle by describing the system in a high level abstract HDL model (without need for detailed design to gate level)  Enables early problem detection since describing functional behavior at high level of abstraction (without complex timing problems associated with gates/transistors)  Therefore, detailed gate level implementation not required before testing can begin.  Technology independent hardware description : – Technology selection is left until the synthesis stage – Synthesis tools automate much of the technology specific decisions (timing, area, driving strength, choice). – Allows designer to concentrate on system function. – New ECAD tools can provide ‘next generation’ implementations of an existing VHDL design database.  VHDL models can be easily reused & adapted.  Many VHDL models of commercial ICs are now available to designers [as Intellectually Property (IP) blocks] and may be easily adapted to suit individual design needs.  VHDL supported by wide range of ECAD tools & development platforms.
  17. 17. Need, Scope, Use and History of VHDL(cont) Module -II (2nd Week) History The Requirement The development of VHDL was initiated in 1981 by the United States Department of Defense to address the hardware life cycle crisis. The cost of reprocuring electronic hardware as technologies became obsolete was reaching crisis point, because the function of the parts was not adequately documented, and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools. The requirement was for a language with a wide range of descriptive capability that would work the same on any simulator and was independent of technology or design methodology. Standardization The standardization process for VHDL was unique in that the participation and feedback from industry was sought at an early stage. A baseline language (version 7.2) was published 2 years before the standard so that tool development could begin in earnest in advance of the standard. All rights to the language definition were given away by the DoD to the IEEE in order to encourage industry acceptance and investment. VHDL 1993 As an IEEE standard, VHDL must undergo a review process every 5 years (or sooner) to ensure its ongoing relevance to the industry. The first such revision was completed in September 1993, and this is still the most widely supported version of VHDL. VHDL 2000 and VHDL 2002 One of the features that was introduced in VHDL-1993 was shared variables. Unfortunately, it wasn't possible to use these in any meaningful way. A working group eventually resolved this by proposing the addition of protected types to VHDL. VHDL 2000 Edition is simply VHDL-1993 with protected types.
  18. 18. VLSI Design(FPGA) process Example: Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Module -II ( 2nd Week) Specifications VHDL description (Your VHDL Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port(clock, reset, encr_decr: in std_logic; key_read: out std_logic); end AES_core; Functional/ Behavioral simulation Post-synthesis simulation Synthesis Implementation (Mapping, Placing & Routing) Timing simulation On chip testing Configuration
  19. 19. Design Simulation and Design Synthesis Module -II (2nd Week) Synthesis Is the process of translating a design description to another level of abstraction, i.e., from behavior to structure. We achieved synthesis by using a Synthesis tool like Foundation Express which outputs a net list. It is similar to the compilation of a high level programming language like C into assembly code Simulation Is the execution of a model in the software environment. During design creation/verification, a design is captured in an RTLlevel (behavioral) VHDL source file. After capturing the design, you can perform a behavioral simulation of the VHDL file to verify that the VHDL code is correct. The code is then synthesized into an gate-level (structural) VHDL netlist. After synthesis, you can perform an optional pre-layout structural simulation of the design. Finally, an EDIF netlist is generated for use in Designer and a VHDL structural post-layout netlist is generated for timing simulation in a VHDL simulator. Design Creation/Verification VHDL Source Entry Enter your VHDL design source using a text editor or a context-sensitive HDL editor. Your VHDL design source can contain RTL-level constructs. Behavioral Simulation Perform a behavioral simulation of your design before synthesis. Behavioral simulation verifies the functionality of your VHDL code. Typically, you use zero delays and a standard VHDL test bench to drive simulation. Synthesis After you have created your behavioral VHDL design source, you must synthesize it. Synthesis transforms the behavioral VHDL file into a gate-level netlist and optimizes the design for a target technology. Simulation Then simulator will check functionality. It means that design and code should be working according to truth table or not. Simulation is just testing the system at software level where as real testing is at hardware level.
  20. 20. VHDL Modelling Styles Module -II (2nd Week) There are three modeling styles:  Behavioral  Data flow  Structural Behavioral Describe how the circuit works is meant to work and let the synthesizer work out the details. This is most useful for Finite State Machines and programs involving sequential statements and processes. Example : XOR-gate entity xor is port (a,b:in std_logic; q:out std_logic); end xor; architecture behavioral of xor is begin process(a,b) begin if (a/=b) then q <= ‘1’; else q <= ‘0’; end if; end process; end behavioral;
  21. 21. VHDL Modelling Styles Module -II (2nd Week) Dataflow Structural In the data flow approach, circuits are described by indicating how the inputs and outputs of built-in primitive components (ex. an and gate) are connected together. In other words we describe how signals (data) flow through the circuit. Structurally defined code assigns a logical function of the inputs to each output. This is most useful for simple combinatorial logic. Example : Xor gate entity xor is port (a,b:in std_logic; q:out std_logic); end xor; entity xor is port (a,b:in std_logic; q:out std_logic); end xor; architecture dataflow of xor is begin q <= a xor b; Or in behavioral data flow style: q <= ‘1’ when a/=b else ‘0’; end dataflow; Example : Xor gate architecture structural of xor is component xor1 is port(x,y:in std_logic; m: out std_logic); end component; signal ai,bi,t3,t4:std_logic; begin u1: inverter port map (a,ai); u2: inverter port map (b,bi); u3: and_gate port map (ai,b,t3); u4: and_gate port map (bi,a,t4); u5: or_gate port map (t3,t4,q); End structural;
  22. 22. Data Types in VHDL Module -II (2nd Week) VHDL provides a number of basic, or scalar, types, and a means of forming composite types. The scalar types include numbers, physical quantities, and enumerations (including enumerations of characters), and there are a number of standard predefined basic types. The composite types provided are arrays and records. VHDL also provides access types (pointers) and files. Scalar Types 1) Integer An integer type is a range of integer values within a specified range. The VHDL standard allows an implementation to restrict the range, but requires that it must at least allow the range –2147483647 to +2147483647. Example : architecture test_int of test is begin process(x) variable a:integer; begin a:=1; --ok a :=-1; --ok a:=1.0; --illegal end test_int; 2) Real The VHDL standard allows an implementation to restrict the range, but requires that it must at least allow the range – 1.0E38 to 1.0E38. This type consists of the real numbers within a simulator-specific . Example architecture test_int of test is begin process(x) variable a:integer; Begin a:=1.3; --ok a:=1; --illegal end test_int;
  23. 23. Data Types in VHDL Module -II (2nd Week) 3) Enumeration An enumeration type is an ordered set of identifiers or characters. The identifiers and characters within a single enumeration type must be distinct, however they may be reused in several different enumeration types. Example type binary is ( on, off); architecture test_enu of test is begin process(x) variable a:binary ; begin a:= on; --ok a:=off; --ok end process; end test_enu; 4) Physical A physical type is a numeric type for representing some physical quantity, such as mass, length, time or voltage. The declaration of a physical type includes the specification of a base unit, and possibly a number of secondary units, being multiples of the base unit. Example type resistance is range 0 to 1000000 units ohm ; -- units kohm =1000 ohm; mohm = 1000kohm; end units;
  24. 24. Data Types in VHDL Module -II (2nd Week) Composite types 1) Arrays An array in VHDL is an indexed collection of elements all of the same type. Arrays may be one-dimensional (with one index) or multidimensional (with a number of indices). In addition, an array type may be constrained, in which the bounds for an index are established when the type is defined, or unconstrained, in which the bounds are established subsequently. Example type word is array (31 downto 0) of bit; type memory is array (address) of word; type transform is array (1 to 4, 1 to 4) of real; type register_bank is array (byte range 0 to 132) of integer; 2) Records VHDL provides basic facilities for records, which are collections of named elements of possibly different types. Example type instruction is record op_code : processor_op; address_mode : mode; operand1, operand2: integer range 0 to 15; end record; Subtypes The use of a subtype allows the values taken on by an object to be restricted or constrained subset of some base type. There are two cases of subtypes. Firstly a subtype may constrain values from a scalar type to be within a specified range (a range constraint). Example: subtype pin_count is integer range 0 to 400; subtype digits is character range '0' to '9'; Secondly, a subtype may constrain an otherwise unconstrained array type by specifying bounds for the indices. For example: subtype id is string(1 to 20); subtype word is bit _vector(31 downto 0);
  25. 25. Objects in VHDL Module -II (2nd Week) An object is a named item in a VHDL description which has a value of a specified type. There are four classes of objects:  Constants.  Variables .  Signals.  Files. 1) Constants Constant declarations with the initializing expression missing are called deferred constants, and may only appear in package declarations . The initial value must be given in the corresponding package body. Example constant e : real := 2.71828; constant delay : Time := 5 ns; constant max_size : natural; 2) Variables A variable is an object whose value may be changed after it is created. The initial value expression, if present, is evaluated and assigned to the variable when it is created. If the expression is absent, a default value is assigned when the variable is created. The default value for scalar types is the leftmost value for the type, that is the first in the list of an enumeration type, the lowest in an ascending range, or the highest in a descending range. If the variable is a composite type, the default value is the composition of the default values for each element, based on the element types. Example variable count : natural := 0; variable trace : trace_array; variable instr : bit_vector(31 downto 0); alias op_code : bit_vector(7 downto 0) is instr(31 downto 24);
  26. 26. Objects & Operators in VHDL Module -II (2nd Week) 3) Signals It is used for communication between VHDL components .Real, Physical signal in the systems are often mapped to VHDL signals. All VHDL signal assignment require either delta cycle or user specified delay before new value is assumed. Example signal a: bit; a <= ‘0’; 4) Files File provide a way for VHDL design communicate with host enviornment.File declaration will make file available for the use to design. It can also open for reading and writing. The package standard defines basic file I/O routines for VHDL types. VHDL supports different classes of operators that operate on signals, variables and constants. The different classes of operators are1) Logical operators The logical operators and, or, nand, nor, xor and not operate on values of type bit or Boolean, and also on onedimensional arrays of these types. For array operands, the operation is applied between corresponding elements of each array, yielding an array of the same length as the result. Logic operators are the heart of logic equations and conditional statements. These are AND, OR, NOT,NAND,NOR,XOR, XNOR 2) Relational operators The relational operators =, /=, <, <=, > and >= must have both operands of the same type, and yield Boolean results. The equality operators (= and /=) can have operands of any type. For composite types, two values are equal if all of their corresponding elements are equal. The remaining operators must have operands which are scalar types or onedimensional arrays of discrete types. These are used in conditional statements. = equal to ; /= not equal to ; < less than ; <= less then or equal to ; > greater than; >= greater than or equal to
  27. 27. Operators in VHDL Module -II (2nd Week) 3) Sign operators The sign operators (+ and –) and the addition (+) and subtraction (–) operators have their usual meaning on numeric operands. The concatenation operator (&) operates on one-dimensional arrays to form a new array with the contents of the right operand following the contents of the left operand. It can also concatenate a single new element to an array, or two individual elements to form an array. The concatenation operator is most commonly used with strings. Example: signal A: bit_vector(5 downto 0); signal B,C: bit_vector(2 downto 0); B <= ‘0’ & ‘1’ & ‘0’; C <= ‘1’ & ‘1’ & ‘0’; A <= B & C; -- A now has “010110” 4) Multiplication operator The multiplication (*) and division (/) operators work on integer, floating point and physical types types. The modulus (mod) and remainder (rem) operators only work on integer types. The absolute value (abs) operator works on any numeric type. Finally, the exponentiation (**) operator can have an integer or floating point left operand, but must have an integer right operand. A negative right operand is only allowed if the left operand is a floating point number. / division mod modulus rem remainder mod & rem operate on integers & result is integer rem has sign of 1st operand and is defined as: A rem B = A – (A/B) * B mod has sign of 2nd operand and is defined as: A mod B = A – B * N -- for an integer N Examples: 7 mod 4 -7 mod 4 7 mod (-4) -7 mod (-4 ) -- has value 3 -- has value –3 -- has value –1 -- has value –3
  28. 28. Operators in VHDL 5) Misc. Operators These are as follows ** exponentiation left operand = integer or floating point right operand = integer only abs absolute value not inversion 6) Shift Operators sll shift left logical (fill value is ‘0’) srl shift right logical (fill value is ‘0’) sla shift left arithmetic (fill value is right-hand bit) sra shift right arithmetic (fill value is left-hand bit) rol rotate left ror rotate right All operators have two operands: left operand is bit vector to shift/rotate right operand is integer for # shifts/rotates - integer same as opposite operator with + integer examples: “1100” sll 1 yields “1000” “1100” srl 2 yields “0011” “1100” sla 1 yields “1000” “1100” sra 2 yields “1111” “1100” rol 1 yields “1001” “1100” ror 2 yields “0011” “1100” ror –1 same as “1100” rol 1 Module -II (2nd Week)
  29. 29. CONDITIONAL STATEMENTS AND LOOPS IN VHDL Module -II (2nd Week) With Select Statements A selected assignment statement is also a concurrent signal assignment statement. It is sequential version of the select statement is the case statement. Syntax with expression select target <= waveform when choice [, waveform when choice ] ; Exampleentity mux4to1 is port ( a,b,c,d : in std_logic; sel: in std_logic_vector (1 downto 0); dout: out std_logic); end mux4to1; architecture whenelse of mux4to1 is begin with sel select dout <= b when "01", c when "10", d when "11", a when others; end select_statement;
  30. 30. CONDITIONAL STATEMENTS AND LOOPS IN VHDL Module -II (2nd Week) When Else Statements When is one of the fundamental concurrent statements. It appears in two forms: when/else and with/select/when. The when-else construct is useful to express logic function in the form of a truth table. Syntaxassignment when condition else assignment when condition else Exampleentity mux4to1 is port ( a,b,c,d : in std_logic; sel: in std_logic_vector (1 downto 0); dout: out std_logic); end mux4to1; architecture whenelse of mux4to1 is begin dout <= b when (sel = "01") else c when (sel = "10") else d when (sel = "11") else a; -- default end process; end whenelse;
  31. 31. CONDITIONAL STATEMENTS AND LOOPS IN VHDL Module -II (2nd Week) If Statement Conditional structure. The if statement in VHDL is a sequential statement that conditionally executes other sequential statements, depending upon the value of some condition. An if statement may optionally contain an else part, executed if the condition is false. Syntax [ label: ] if condition1 then sequence-of-statements elsif condition2 then elsif condition3 then else sequence-of-statements end if [ label ] ; Example-Mux architecture behavioral of mux is begin process (sel, a, b) begin if sel = '1' then f <= a; else f <= b; end if; end process;
  32. 32. CONDITIONAL STATEMENTS AND LOOPS IN VHDL Module -II (2nd Week) Case Statements Execute one specific case of an expression equal to a choice. The choices must be constants of the same discrete type as the expression. The selection expression must result in either a discrete type, or a one dimensional array of characters. The alternative whose choice list includes the value of the expression is selected and the statement list executed. Note that all the choices must be distinct, that is, no value may be duplicated. Syntax[ label: ] case expression is when choice1 => sequence-of-statements when choice2 => sequence-of-statements when others => sequence-of-statements end case [ label ] ; Examplearchitecture Behavioral of mux is begin process(a,b,c,d,sel) begin case sel is when "00" => o <= a; when "01" => o <= b; when "10" => o <= c; when "11"=> o <= d; when others=> null; end case; end process; end Behavioral;
  33. 33. CONDITIONAL STATEMENTS AND LOOPS IN VHDL Module -II (2nd Week) Loop Statements VHDL has a basic loop statement, which can be augmented to form the usual while and for loops seen in other programming languages. Three kinds of iteration statements. Syntax[ label: ] loop sequence-of-statements -- use exit statement to get out end loop [ label ] ; [ label: ] for variable in range loop sequence-of-statements end loop [ label ] ; [ label: ] while condition loop sequence-of-statements end loop [ label ] ; Exampleentity EX is port (A : in std_logic_vector(0 to 3); SEL : in integer range 0 to 3; Z : out std_logic); end EX; architecture RTL of EX is begin WHAT: process (A, SEL) begin for I in 0 to 3 loop if SEL = I then Z <= A(I); end if; end loop; end process WHAT; end RTL;
  34. 34. STRUCTURAL STYLE Module -III (3rd Week) Structural Style of Modelling         Structural VHDL describes the arrangement and interconnection of components. Structural descriptions can show a more concrete relation between code and physical hardware. Structural descriptions show interconnects at any level of abstraction. The component instantiation is one of the building blocks of structural descriptions. The component instantiation process requires component declarations and component instantiation statements. Component instantiation declares the interface of the components used in the architecture. At instantiation, only the interface is visible. The internals of the component are hidden. Components The components and signals are declared within the architecture body, architecture architecture_name of NAME_OF_ENTITY is -- Declarations component declarations signal declarations begin -- Statements component instantiation and connections : end architecture_name;
  35. 35. STRUCTURAL STYLE Module -III (3rd Week) Component declaration Before components can be instantiated they need to be declared in the architecture declaration section or in the package declaration. The component declaration consists of the component name and the interface (ports). The syntax is as follows: component component_name [is] [port (port_signal_names: mode type; port_signal_names: mode type; : port_signal_names: mode type);] end component [component_name]; The component name refers to either the name of an entity defined in a library or an entity explicitly defined in the VHDL file.The list of interface ports gives the name, mode and type of each port, similarly as is done in the entity declaration. Example component OR2 port (in1, in2: in std_logic; out1: out std_logic); end component;
  36. 36. STRUCTURAL STYLE Module -III (3rd Week) Component Instantiation and interconnections The component instantiation statement references a component that can be :Previously defined at the current level of the hierarchy or Defined in a technology library (vendor’s library). The syntax for the components instantiation is as follows, instance name : component name port map (port1=>signal1, port2=> signal2,… port3=>signaln); The instance name or label can be any legal identifier and is the name of this particular instance. The component name is the name of the component declared earlier using the component declaration statement. The port name is the name of the port and signal is the name of the signal to which the specific port is connected. The above port map associates the ports to the signals through named association. Example: component NAND2 port (in1, in2: in std_logic; out1: out std_logic); end component; signal int1, int2, int3: std_logic; architecture struct of EXAMPLE is U1: NAND2 port map (A,B,int1); U2: NAND2 port map (in2=>C, in2=>D, out1=>int2); U3: NAND3 port map (in1=>int1, int2, Z); Benefits of Structural Style  Circuits can be described like a netlist  Components can be customized  Large, regular circuits can be created
  37. 37. COUNTERS Module -III (3rd Week) Counters A counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. In electronics, counters can be implemented quite easily using registertype circuits such as the flip flop, and a wide variety of designs exist, e.g.: Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops. Synchronous counter – all state bits change under control of a single clock. Decade counter – counts through ten states per stage. Up–down counter – counts both up and down, under command of a control input. Ring counter – formed by a shift register with feedback connection in a ring. Johnson counter – a twisted ring counter. Cascaded counter. Johnson counter The Johnson counter can be made with a series of D flip-flops or with a series of J-K flip flops. Here Q3 and Q3 are fed back to the J and K inputs with a “twist”.
  38. 38. COUNTERS Module -III (3rd Week) The disadvantage to this counter is that it must be preloaded with the desired pattern (usually a single 0 or 1) and it has even fewer states than a Johnson counter (n, where n = number of flip-flops. On the other hand, it has the advantage of being self-decoding with a unique output for each state. Up/Down Counter entity updown is Port ( clr,clk,up : in STD_LOGIC; count : inout STD_LOGIC_VECTOR(3 downto 0)); end updown; architecture Behavioral of updown is signal output: std_logic_vector(3 downto 0); begin process(clr,clk,up) begin if clr = '1' then output <= "0000"; elsif(clk'event and clk ='1') then if up ='0' then output <= output + 1; else output <= output -1; end if; end if; end process; count <= output; end Behavioral;
  39. 39. COUNTERS Module -III (3rd Week) BCD Counter A 4-bit BCD-counter built with JK-flip flops. This is an asynchronous implementation of a cascadable, 4-bit, binary-coded decimal counter. In total, the circuits needs just the four flip flops and one additional AND gate. VHDL Code: entity bcd is Port ( clr,clk : in STD_LOGIC; count : inout STD_LOGIC_VECTOR (3 downto 0)); end bcd ; architecture Behavioral of mod16 is begin process(clr,clk) begin if(clk'event and clk ='1') then if (clr = '1' or count >= 9) then count <="0000"; else count <= count + 1; end if; end if; end process; end Behavioral;
  40. 40. Flip Flops & Latches Module -III (3rd Week)  A flip-flop or latch is a circuit that has two stable states and can be used to store state information.  The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs.  Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.  Memory means circuit remains in one state after condition that caused the state is removed.  Two outputs designated Q and Q-Not that are always opposite or complimentary.  When referring to the state of a flip flop, referring to the state of the Q output.  Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state, and such a circuit is described as sequential logic  When used in a finite-state machine the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs.)  It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.  Flip-flops can be either simple (transparent or opaque) or clocked(synchronous or edge-triggered); the simple ones are commonly called latches.  The word latch is mainly used for storage elements, while clocked devices are described as flip-flops.
  41. 41. Flip Flops Module -III (3rd Week) R-S FLIP-FLOP When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low. Symbol and Diagram and truth table Basic flip-flop circuit with NOR gates Basic flip-flop circuit with NAND gates Truth table
  42. 42. Flip Flops Module -III (3rd Week) JK flip-flop The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop. The characteristic equation of the JK flip-flop is: Symbol and Diagram Graphical symbol Logic diagram Transition table
  43. 43. Flip Flops Module -III (3rd Week) D flip-flop The D flip-flop is the most common flip-flop in use today. It is better known as data or delay flip-flop (as its output Q looks like a delay of input D).The Q output takes on the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise. Symbol and Diagram Graphical symbol Logic diagram with NAND gates Transition table
  44. 44. Shift Registers Module -IV (4th Week) A register is a digital circuit with two basic functions: Data Storage and Data Movement  A shift register provides the data movement function  A shift register “shifts” its output once every clock cycle A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs connected together in such a way that the data is shifted from one device to another when the circuit is active. Shift Register Applications Communications  UART Converting between serial data and parallel data Temporary storage in a processor Scratch-pad memories Some arithmetic operations Multiply, divide Some counter applications  Johnson counter Ring counter  LSFR counters Time delay devices and more …
  45. 45. Shift Registers Shift Register Characteristics Types  Serial-in, Serial-out  Serial-in, Parallel-out  Parallel-in, Serial-out  Parallel-in, Parallel-out  Universal Direction     Left shift Right shift Rotate (right or left) Bidirectional Data Movement The bits in a shift register can move in any of the following manners Module -IV (4th Week) n-bit shift register
  46. 46. Shift Registers Module -IV (4th Week) Serial-In Serial-Out     Data bits come in one at a time and leave one at a time. One Flip-Flop for each bit to be handled. Movement can be left or right, but is usually only a single direction in a given register Asynchronous preset and clear inputs are used to set initial values. n-bit shift register
  47. 47. Shift Registers Serial-to-Parallel Conversion We often need to convert from serial to parallel e.g., after receiving a series transmission. The diagrams at right illustrate a 4-bit serial-in parallel-out shift register. Note that we could also use the Q of the right-most Flip-Flop as a serial-out output Module -IV (4th Week)
  48. 48. Shift Registers Module -IV (4th Week) Parallel-to-Serial Conversion We use a Parallel-in Serial-out Shift Register. The DATA is applied in parallel form to the parallel input pins PA to PD of the register. It is then read out sequentially from the register one bit at a time from PA to PD on each clock cycle in a serial format. One clock pulse to load. Four pulses to unload. n-bit shift register
  49. 49. Shift Registers Module -IV (4th Week) Parallel in parallel out All data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it, then output
  50. 50. Finite State Machines Module -IV (4th Week) A finite state machine a set of states and two functions called the next state function and the output function.  The set of states corresponding to all the possible combinations of the internal storage  If there are n bits of storage , there are 2n possible states.  The next state function is a combinational logic function that given the inputs and the current state, determines the next state of the system.  The output function produces a set of outputs from the current state and the inputs.  Sequential circuits  primitive sequential elements  combinational logic  Models for representing sequential circuits  Finite-state machines (Moore and Mealy)  Basic sequential circuits revisited  Shift registers  Counters  Design procedure  State diagrams  State transition table  Next state functions  Hardware description languages These are the topics that will be discussed in this chapter. Of course the next state depends on the current state and the input values. The FSMs fall into two categories: Moore and Mealy machines. Also we will look at how inputs are handled in sequential systems. Still registers and counters are key parts of the sequential circuits.
  51. 51. Finite State Machines Module -IV (4th Week) Finite state machine design procedure      Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic Hardware description languages We start with simple FSMs like counters and shift registers, where states are outputs directly. We should differentiate Moore and Mealy models. With either model, we should be able to design a FSM. Counters are simple finite state machines  Counters  proceed through well-defined sequence of states in response to enable  Many types of counters: binary, BCD, Gray-code  3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...  3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ... In the case of a 3bit up counter, every clock tick will make a transition without any inputs. In this case the numbers follow binary coding; hence it is called a binary counter.
  52. 52. Finite State Machines Module -IV (4th Week) Example: FSM design procedure: state diagram to encode state transition table  Tabular form of state diagram  Like a truth-table (specify output for all input combinations)  Encoding of states: easy for counters – just use value For the 3-bit up counter, here is the state transition table. It’s like there are three inputs and three outputs. In this case the literals for states are the inputs for the state transition. If there are other outside inputs, those should be also written in the table.
  53. 53. Finite State Machines Implementation D flip-flop for each state bit Combinational logic based on encoding Module -IV (4th Week) VHDL notation to show function represents an input to D-FF These are K-maps for three outputs. <= is a non-blocking assignment operator. That is, all values (N1, N2, N3) are changed at the same time, not sequentially.
  54. 54. Mini Projects Based on FPGA Module -V (5th & 6th Week) Each student after completing 4 modules have to start industry standard project in the 5th week, the project report should follow the given hierarchy  Design Specification Analysis :  Creating the Design Architecture  Partitioning the design  RTL coding in VHDL  RTL Functional Verification  RTL Synthesis  Place & Route the netlist  Implementing the design onto the FPGA Board  Verifying design on FPGA Board The evaluation of the project will be based on the above said hierarchy of the design, the grading of the project also includes the performance of each student in the two tests conducted and also attendance.
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