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Sdr 2
 

Sdr 2

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sdr parts

sdr parts

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    Sdr 2 Sdr 2 Document Transcript

    • Wireless Information Technology Lab Experimental Software Defined Radio Platforms Bertalan Eged, et. al. Eged, Budapest University of Technology and Economics Department Dep artment of Microwave Telecommunications H-1111 Budapest, Goldmann Gy. tér 3. Gy. TEL: +36 1 463-3514 FAX: +36 1 463-3289 email: beged @mht .bme.hu 463-3514 beged@mht.bme. First test platform based on separate demo boards: FPGA DAC The first experimental platform allowed us to build up the required development system and try the basic technological components to implement SDR platforms, including: •DSP program design and implementation •FPGA firmware development •Serial communication with ASIC up-converters •DAC high-speed clocking and timing •IF signal oversampling with interpolating DAC One of our fist application program: GSM-EDGE modulator. DSP DUC The picture shows the histogram of this 8PSK signal. Experimental SDR platform based on ADSP21065 floatingpoint signal processor, Xilinx XCS40XL (Spartan I) FPGA, AD6622 digital up-converter, AD9772A interpolating DAC In the next phase we integrate the DAC, the DUCs and the FPGA on one PCB module. Integrated SDR platform containing: ADSP21160 SHARC floating-point processor, XC2S50 (Spartan II) FPGA, 4X AD6622 DUCs, PIC16F877 micro controller Result of the application developments includes complete set of higher level vector modulations: 4PSK 16QAM 8PSK 32QAM Technology enhancements: •Integrated uC based platform controller •Direct DMA interface to the DSP bus •FPGA (re)programming with uC •DUC (re)programming trough the platform controller •Implementation of a control scripting possibility 8QAM 64QAM Eye diagram of the I-channel signal of the 32QAM vector modulator For more information visit our website: website: http://wit.mht. bme.hu http://wit.mht. bme.hu