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Thesis presentation Thesis presentation Presentation Transcript

  • “ Design, Analysis and Simulations of a Si Schottky Diode Based Sampling Circuit for 40 Gbps ETDM Demultiplexer Circuit “ Supervisors: Prof. Dr. techn. Peter Russer Jung Han Choi, M.S. Master Thesis: Septiaji Eko Nugroho Master of Science in Microwave Engineering (MSMWE) Program Institute for High Frequency Engineering
  • Layout
    • Sampling Circuit for Demultiplexer
      • Multiplexing Overview
      • The Demultiplexer Circuit
      • The Sampling Theory and The Undersampling Technique for Demultiplexer
      • Sampling Circuit for Demultiplexer
    • Driving Requirements and Components
      • Driving Requirements
      • The Components
    • Design, Analysis and Simulations
      • The Rule of the Design
      • Bandwidth Optimization: Analytic and Simulation
      • Layout Design and Simulation
      • Flip Chip Bonding Effect
      • Effect of Oscillator Phase Difference
    • Conclusions and Future Works
  • 1. Sampling Circuit for Demultiplexer
    • Multiplexing/Demultiplexing Overview
    • The Demultiplexer Circuit in ETDM system
    • The Sampling Theory and The Undersampling Technique for Demultiplexer
    • Sampling Circuit for Demultiplexer
  • Multiplexing/Demultiplexing Overview
    • Backgrounds:
    • Optical fiber is able to transmit THz of signal
    • The bit rate in the fiber was limited, caused by the speed of electronic components (i.e. 10 Gbps at 1995)
    • To increase the operation speed of the fiber : Multiplexing technique is introduced:
      • Time Division Multiplexing (TDM)
        • ETDM: Electronic TDM
        • OTDM: Optical TDM
      • Frequency Division Multiplexing (FDM)/Wavelength Division Multiplexing (WDM)
    1. Sampling Circuit for Demultiplexer
  • The Demultiplexer Circuit for ETDM system The Demultiplexer Circuit for ETDM system 1. Sampling Circuit for Demultiplexer Diagram of 4-Way Demultiplexer Diagram of Optical Receiver
  • The Sampling Theory and The Undersampling Technique for Demultiplexer (1) 1. Sampling Circuit for Demultiplexer
  • The Sampling Theory and The Undersampling Technique for Demultiplexer (2) Input : Ideal NRZ signal NRZ pulse: Output of the first channel: is “1” or “0” 1. Sampling Circuit for Demultiplexer
  • The Sampling Theory and The Undersampling Technique for Demultiplexer (3) For 1:2 Demultiplexer: Output of the first channel: Output of the second channel: (Undersampling Technique) 1. Sampling Circuit for Demultiplexer
  • The Sampling Theory and The Undersampling Technique for Demultiplexer (4) Output 1. Sampling Circuit for Demultiplexer
  • The Sampling Circuit for Demultiplexer (1)
    • Sampling Circuit Topology:
    • Based on Sampling Circuit of the Oscilloscope
    • Using Double Diode Configuration
    • Very Symmetric
    1. Sampling Circuit for Demultiplexer
  • The Sampling Circuit for Demultiplexer (2)
    • Basic operation:
    • Vbias will charge Chold so that the diode will be in reverse bias
    • The strobe turn on the diode in a very small span time
    • In this span time, the charge will be transferred from the input into the Chold
    1. Sampling Circuit for Demultiplexer
  • 2. Driving Requirements and Circuit Components
    • Driving Requirements
    • Circuit Components
  • Driving Requirements 2. Circuit Requirements and Components Broadband Characteristic is Important Circuit bandwidth > 40 GHz is necessary Spectrum of 40 Gbps NRZ signal PRBS 2 7 -1
  • The Components in the Design 2. Circuit Requirements and Components
    • Infineon Schottky Diode Double Configuration
    • Oscillators 20 GHz max 1 Vpp
    • DC Bias
    • Alumina ( Al 2 O 3 ) Substrates
    • Hold Capacitors
  • Infineon Schottky Diode Double Configuration 2. Circuit Requirements and Components
    • General Properties:
    • Using Flip-Chip Interconnections
    • Cjo=30 fF, Rs=10 Ohm
    • Max forward current = 25 mA
    • Modeled by Root Diode Model in the ADS:
    • Large signal table based model
    • Generated from measured DC and small signal S-Parameters
  • DC Characteristic of the Diode Model 2. Circuit Requirements and Components We define turn-on point of the diode is 480 mV
  • Flip-Chip Bonding AuSn (1) 2. Circuit Requirements and Components Equivalent Model Resonance frequency *): *)Chun-Long Wang and Ruey-Beei Wu, “A Locally matching Technique for Broadband Flip-chip Transition Design,” IEEE Trans. Microwave Theory Tech. , pp. 1399, February 2002 . Using L=103 pH, C=45 fF, Zo=50 Ohm f res =76.9 GHz Height= 5 um Diameter=50 um
  • Flip-Chip Bonding AuSn (2) 2. Circuit Requirements and Components Equivalent Model*) The double diode pad C=20 fF *) Jung Han Choi, C.-J. Weiske, G.R. Olbrich, P. Russer, “Flip-chip bonded Si Schottky Sampling Circuits for High Speed Demultiplexer”, Microwave Symposium Digest, 2003 IEEE MTT-S International , vol. 3, pp. 1515-1518, 8-13 June 2003.
  • 3. Design, Analysis and Simulation
    • The Rule of Design
    • Bandwidth Optimization: Analytic and Simulation
    • Layout Design and Simulation
    • Operation in Lower Speed
    • Flip Chip Bonding Effect
    • Effect of Oscillator Phase Difference
  • Circuit Topology
    • Oscillator is used
    • Flip-chip bonding model is included
    • Input Bit pattern is PRBS 2 7 -1
    3. Design, Analysis and Simulation
  • Basic Operation : Turning On the Diode (1) Proper operation Turn-on point = 480 mV 3. Design, Analysis and Simulation
  • Basic Operation : Turning On the Diode (2)
    • Unproper operation:
    • Diode voltage always above the turn on point: all bits will be passed
    • Caused by too small Rbias (e.g. 15 Ohm)
    3. Design, Analysis and Simulation
  • Simulation Results Input 40 Gbps PRBS 2 7 -1 Output Channel 1 Output Channel 2 3. Design, Analysis and Simulation
  • Eye Diagram of the 20 Gbps Output Signal
    • Vertical Eye opening= 45 mV
    3. Design, Analysis and Simulation 50 ps 45 mV
  • Bandwidth Optimization (1) - Analytic Using KCL on all nodes:
    • Flip-chip bonding is neglected
    • Diodes are turned-on
    3. Design, Analysis and Simulation
  • Bandwidth Optimization (2) - Analytic Transfer function: Define : 3. Design, Analysis and Simulation
  • Bandwidth Optimization (3) - Analytic Transfer function: It has low pass characteristic, with cutoff frequency: or 3. Design, Analysis and Simulation
  • Bandwidth Optimization (4) – S-Parameter Simulation 3. Design, Analysis and Simulation
  • Bandwidth Optimization (5) – Impulse Response 3. Design, Analysis and Simulation
    • Smaller Chold leads higher bandwidth
    • Bigger Chold will reduce the fringing voltage
    5.2 0.1 6.6 0.3 7.2 0.5 FWHM (ps) Chold (pF)
  • Bandwidth Optimization (6) – Comparison 3. Design, Analysis and Simulation
  • Layout Design (1)
    • Substrate Thickness : 10 mil
    • Dielectric : 9.9
    • Permeability : 1.0
    • Metal conductivity : 4.1E+07 S/m ( Gold )
    • Metal tangent loss : 0.00
    • Metal thickness : 6 um
    • Metal Roughness : 0.0
    • Resistive layer : 40 Ohm/square
    Alumina Substrate Properties 3. Design, Analysis and Simulation
  • Layout Design (2)-SC_0609
    • Intrinsic Circuit:
    • Brown-Conductor layer
    • Green-Resistive layer
    • Size 1700 x 1700 (um)
    3. Design, Analysis and Simulation
  • Layout Design (3)-SC_0609
    • Major Problem:
    • Resonance at 38 GHz using Chold 0.1 pF, and 29 GHZ using Chold 0.2 pF
    • Caused by the effect of the distance between capacitor and the diode (675 um)
    • Then the distance must be reduced
    ADS Co-simulation Result 3. Design, Analysis and Simulation
  • Layout Design (4)-SC_0110 1000 um x 1400 um. Distance betwen capacitor and diode is 250 um 3. Design, Analysis and Simulation
  • Layout Design (5)-SC_0110 55 GHz bandwidth with linear phase is achieved using Chold 0.1 pF. ADS Co-simulation Result: 3. Design, Analysis and Simulation
  • Output Eyewaveform
    • Infineon Schotkky Diode
    • Output peak=32 mV
    • Eye_opening=18 mV
    • There is distortion
    • Ideal Diode
    • Output peak=45 mV
    • Eye_opening=30 mV
    • The distortion is small
    3. Design, Analysis and Simulation
  • Operation in Lower Speed 20 Gbps DEMUX 1:2 Chold=0.35 pF 10 Gbps DEMUX 1:2 Chold=0.65 pF 3. Design, Analysis and Simulation
  • Flip-Chip Bonding Effect (1) 3. Design, Analysis and Simulation
  • Flip-Chip Bonding Effect (2)-40 Gbps Input Without flipchip With flipchip 3. Design, Analysis and Simulation
  • Flip-Chip Bonding Effect (3)-86 Gbps Input Without flipchip With flipchip Input 86 Gbps RZ PRBS 2 7 -1 Output Eyewaveform Flip-chip bonding highly affects the 86 Gbps performance. 3. Design, Analysis and Simulation
  • Effect of Asymmetry: Oscillator Phase Difference (1)
    • Portion of the Oscillators on the output signal:
    • The phase difference will add sinusoidal signal as distortion in the output. The greater the phase difference, the greater the distortion
    3. Design, Analysis and Simulation
  • Effect of Asymmetry: Oscillator Phase Difference (2) 10 o phase difference 5 o phase difference 15 o phase difference Up to 5 o difference can be tolerated 3. Design, Analysis and Simulation
  • 4. Conclusions and Future Works
    • Conclusions
    • Future Works
  • Conclusions (1)
    • Sampling circuit for demultiplexer 1:2 with input ETDM 40 Gbps NRZ has been designed, analyzed and simulated.
    • The bandwidth analysis has excellent agreement with the simulation up to 50 GHz.
    • To avoid resonance in the desired passband, the distance between capacitor and the diode should be minimized.
    • With Chold 0.1 pF, cutoff frequency of 55 GHz with linear phase are achieved. (SC_0110)
    • The output amplitude of 32 mV and eye opening of 18 mV are achieved.
    • The sampling circuit works well in lower bit rate with excellent output eye diagram (20 Gbps and 10 Gbps input).
    4. Conclusions and Future Works
  • Conclusions (2)
    • The flip-chip bonding affects the bandwidth of the circuit above 50 GHz. It greatly affects the circuit with 86 Gbps input. But it doesn‘t contribute significant effect to the circuit with 40 Gbps input.
    • The oscillator phase difference of 5 o can be tolerated in this circuit.
    4. Conclusions and Future Works
  • Future Works
    • Choosing better diode, which has smaller zero bias junction capacitance, Cj0 lower than 10 fF is recommended for 40 Gbps operation.
    • The real capacitor model with self resonance frequency (SRF) more than 50 GHz should be included, with its interconnection
    • Compensating the effect of the flip-chip bonding for operation above 40 Gbps
    • Extending the circuit into the desired size of the complete circuit
    4. Conclusions and Future Works
  • Thank You! Vielen Dank! Terimakasih! Maturnuwun! Syukron!