By : Balbir  Virdi
 
<ul><li>Instruction cycle  </li></ul><ul><li>Instruction cycle is defined as the time required to complete the execution o...
<ul><li>Memory  is made up of semiconductor material used to store the programs and data. Three types of memory is, </li><...
EPROM AND STATIC RAM: <ul><li>  Typical  semiconductor memory IC will have n address pins, m data pins (or output pins). <...
Memory IC’s
DECODER <ul><li>It is used to select the memory chip of processor during the execution of a program. No. of IC's used for ...
<ul><li>2:4 </li></ul><ul><li>TRUTH TABLE </li></ul>
<ul><li>3:8 </li></ul><ul><li>TRUTH TABLE </li></ul>
Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processo...
<ul><li>Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 ...
<ul><li>In this system the entire 16 address lines of the processor are connected to address input pins of memory IC in or...
EXAMPLE 2 <ul><li>Consider a system in which the available 64kb memory space is equally divided between EPROM and RAM. Int...
The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the processor are connected to 15 address p...
EXAMPLE-3 <ul><li>Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface ...
 
<ul><li>The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RA...
The address allotted to each memory IC is shown in following table.
EXAMPLE-4 <ul><li>Consider a system in which the 64kb memory space is implemented using eight numbers of 8kb memory. Inter...
 
 
Programming model <ul><li>Programming model is a conceptual representation of  a real object. It can take any form, such a...
 
ADDRESSING MODES  OF 8085 <ul><li>To perform any operation, we have to give the  corresponding instructions to the micropr...
<ul><li>The method by which the address of source of data or the address of destination of result is given in the  instruc...
Types of Addressing Modes <ul><li>Intel 8085 uses the following addressing modes: </li></ul><ul><li>1. Direct Addressing M...
Direct Addressing Mode <ul><li>In this mode, the address of the operand is given in the instruction itself.  </li></ul><ul...
Register Addressing Mode <ul><li>In this mode, the operand is in general purpose register. </li></ul><ul><li>MOV is the op...
Register Indirect Addressing Mode <ul><li>In this mode, the address of operand is specified by a register </li></ul><ul><l...
Immediate Addressing Mode <ul><li>In this mode, the operand is specified within the instruction itself.  </li></ul><ul><li...
Implicit Addressing Mode <ul><li>If address of source of data as well as address of destination of result is fixed, then t...
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Memory intrface and addrs modes

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Transcript of "Memory intrface and addrs modes"

  1. 1. By : Balbir Virdi
  2. 3. <ul><li>Instruction cycle </li></ul><ul><li>Instruction cycle is defined as the time required to complete the execution of an instruction. 8085 instruction cycle consist of one to six machine cycle or one to six operation. </li></ul><ul><li>Machine cycle is defined as the time required to complete one operation of accessing memory, I/O or Acknowledging an external request. This cycle may consist of three to six T cycle. </li></ul><ul><li>T-state is defined as one subdivision of the operation performed in one clock period . Each T-state is precisely equal to one clock period. These two terms are often used synonymously. </li></ul>
  3. 4. <ul><li>Memory is made up of semiconductor material used to store the programs and data. Three types of memory is, </li></ul><ul><li>Process memory </li></ul><ul><li>Primary or main memory </li></ul><ul><li>Secondary memory </li></ul>
  4. 5. EPROM AND STATIC RAM: <ul><li>  Typical semiconductor memory IC will have n address pins, m data pins (or output pins). </li></ul><ul><li>Having two power supply pins (one for connecting required supply voltage (V and the other for connecting ground). </li></ul><ul><li>The control signals needed for static RAM are chip select (chip enable), read control (output enable) and write control (write enable). </li></ul><ul><li>The control signals needed for read operation in EPROM are chip select (chip enable) and read control (output enable). </li></ul>
  5. 6. Memory IC’s
  6. 7. DECODER <ul><li>It is used to select the memory chip of processor during the execution of a program. No. of IC's used for decoder is, </li></ul><ul><li>2-4 decoder (74LS139) </li></ul><ul><li>3-8 decoder (74LS138) </li></ul>
  7. 8. <ul><li>2:4 </li></ul><ul><li>TRUTH TABLE </li></ul>
  8. 9. <ul><li>3:8 </li></ul><ul><li>TRUTH TABLE </li></ul>
  9. 10. Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processor. The memory capacity is 64 Kbytes. i.e. 2^n = 64 x 1000 bytes where n = address lines. So, n = 16. In this system the entire 16 address lines of the processor are connected to address input pins of memory IC in order to address the internal locations of memory. The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground). Since the processor is connected to EPROM, the active low RD pin is connected to active low output enable pin of EPROM. The range of address for 64 Kbytes EPROM is 0000H to FFFFH.
  10. 11. <ul><li>Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processor. </li></ul><ul><li>The memory capacity is 64 Kbytes. i.e. </li></ul><ul><li>2^n = 64 x 1000 bytes where n = address lines. </li></ul><ul><li>So, n = 16. </li></ul>
  11. 12. <ul><li>In this system the entire 16 address lines of the processor are connected to address input pins of memory IC in order to address the internal locations of memory. </li></ul><ul><li>The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground). </li></ul><ul><li>Since the processor is connected to EPROM, the active low RD pin is connected to active low output enable pin of EPROM. </li></ul><ul><li>The range of address for 64 Kbytes EPROM is 0000H to FFFFH. </li></ul>
  12. 13. EXAMPLE 2 <ul><li>Consider a system in which the available 64kb memory space is equally divided between EPROM and RAM. Interface the EPROM and RAM with 8085 processor. </li></ul>
  13. 14. The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the processor are connected to 15 address pins of both EPROM and RAM. The unused address line A15 is used as to chip select. If A15  is 1, it select RAM and If  A15  is 0, it select EPROM. Inverter is used for selecting the memory. The memory used is both Ram and EPROM, so the low RD and WR pins of processor are connected to low WE and OE pins of memory respectively. The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 8000H to FFFFH.
  14. 15. EXAMPLE-3 <ul><li>Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor. </li></ul>
  15. 17. <ul><li>The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM. </li></ul><ul><li>Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are connected to 13 address pins of all the memory. </li></ul><ul><li>The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chip select signals. </li></ul><ul><li>These four chip select signals can be used to select one of the four memory IC at any one time. </li></ul><ul><li>The address line A15 is used as enable for decoder. </li></ul>
  16. 18. The address allotted to each memory IC is shown in following table.
  17. 19. EXAMPLE-4 <ul><li>Consider a system in which the 64kb memory space is implemented using eight numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor. </li></ul>The total memory capacity is 64Kb. So, let 3 numbers of 8Kb EPROM and 5 numbers of 8Kb RAM. Each 8kb memory requires 13 address lines. So the address line A0 - A12 of the processor are connected to 13address pins of all the memory lCs. The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to generate eight chip select signals. These eight chip select signals can be used to select one of the eight memories at any one time.
  18. 22. Programming model <ul><li>Programming model is a conceptual representation of a real object. It can take any form, such as text description, a drawing, or a built structure. Like the architecture model of a building, microprocessor can be represented in terms of its physical electronic components and information needed to write programs. The programming model consist of some segments of the ALU and the registers. </li></ul>
  19. 24. ADDRESSING MODES OF 8085 <ul><li>To perform any operation, we have to give the corresponding instructions to the microprocessor. In each instruction, programmer has to specify 3 things: </li></ul><ul><li>Operation to be performed. </li></ul><ul><li>Address of source of data. </li></ul><ul><li>Address of destination of result. </li></ul>
  20. 25. <ul><li>The method by which the address of source of data or the address of destination of result is given in the instruction is called Addressing Modes. </li></ul><ul><li>The term addressing mode refers to the way in which the operand of the instruction is specified. </li></ul>
  21. 26. Types of Addressing Modes <ul><li>Intel 8085 uses the following addressing modes: </li></ul><ul><li>1. Direct Addressing Mode </li></ul><ul><li>2. Register Addressing Mode </li></ul><ul><li>3. Register Indirect Addressing Mode </li></ul><ul><li>4. Immediate Addressing Mode </li></ul><ul><li>5. Implicit Addressing Mode </li></ul>
  22. 27. Direct Addressing Mode <ul><li>In this mode, the address of the operand is given in the instruction itself. </li></ul><ul><li>Here , </li></ul><ul><li>LDA is the operation. </li></ul><ul><li>2500 H is the address of source. </li></ul><ul><li>Accumulator is the destination. </li></ul>LDA 2500 H Load the contents of memory location 2500 H in accumulator.
  23. 28. Register Addressing Mode <ul><li>In this mode, the operand is in general purpose register. </li></ul><ul><li>MOV is the operation. </li></ul><ul><li>B is the source of data. </li></ul><ul><li>A is the destination. </li></ul>MOV A, B Move the contents of register B to A.
  24. 29. Register Indirect Addressing Mode <ul><li>In this mode, the address of operand is specified by a register </li></ul><ul><li>MOV is the operation. </li></ul><ul><li>M is the memory location specified by </li></ul><ul><li>H-L register pair. </li></ul><ul><li>A is the destination register pair. </li></ul>MOV A, M Move data from memory location specified by H-L pair to accumulator.
  25. 30. Immediate Addressing Mode <ul><li>In this mode, the operand is specified within the instruction itself. </li></ul><ul><li>MVI is the operation. </li></ul><ul><li>05 H is the immediate data (source). </li></ul><ul><li>A is the destination. </li></ul>MVI A, 05 H Move 05 H in accumulator.
  26. 31. Implicit Addressing Mode <ul><li>If address of source of data as well as address of destination of result is fixed, then there is no need to give any operand along with the instruction. </li></ul><ul><li>CMA is the operation. </li></ul><ul><li>A is the source. </li></ul><ul><li>A is the destination. </li></ul>CMA Complement accumulator.

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