Intro to cao &store program

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  • Intro to cao &store program

    1. 1. 4 th SEM(CSE) COMPUTER ARCHITECTURE AND ORGANIZATION - M. MORRIS MANO - J.P. Hayes
    2. 2. UNIT-I General System Architecture
    3. 3. Elements Of Computers <ul><li>Every Computer contains the following components:- </li></ul><ul><ul><ul><li>A processor able to interpret and execute programs. </li></ul></ul></ul><ul><ul><ul><li>A memory for storing the programs and data they process. </li></ul></ul></ul><ul><ul><ul><li>Input/Output equipment for transferring information between the computer and the outside world . </li></ul></ul></ul>
    4. 4. Central Processing unit Program Control Arithmetic Logic Unit MAIN MEMORY Input –Output equipment Instructions data MAIN COMPONENTS OF MACHINE COMPUTATIONS
    5. 5. <ul><li>A computer has Several key components :- </li></ul><ul><ul><li>Main Memory corresponds to the paper used in the manual calculations. Its purpose is to store instructions and data. </li></ul></ul><ul><ul><li>Computers brain is its Central Processing unit (CPU). </li></ul></ul><ul><ul><ul><li>It contains a Program Control Unit (also called as instruction unit) whose function is to fetch instructions from memory and interpret them. </li></ul></ul></ul><ul><ul><ul><li>An Arithmetic Logic Unit(ALU) of Part CPU’s data-processing or execution unit, carries out the instructions. </li></ul></ul></ul><ul><ul><li> </li></ul></ul>
    6. 6. <ul><li>NOTE :- ALU is so called because many instructions specify either arithmetic operations or various nonnumerical operations that corresponds to logical reasoning and decision making. </li></ul>
    7. 7. DIGITAL COMPUTERS <ul><li>Digital computer is a digital system that perform various computational tasks. The word “digital” implies that information in the computer is represented by variables that take a limited number of discrete values. </li></ul><ul><li>These values are processed internally by components that can maintain a limited number of discrete states. </li></ul><ul><li>DIGITAL COMPUTERS function more reliably if only two values states are used. </li></ul><ul><li>It is not practical to build computers to handle symbolic or decimal data directly. </li></ul><ul><li>Computers process data in binary form i.e, two symbols 0 and1 called bits (binary digits) . </li></ul>
    8. 8. <ul><li>Because of the fact that Computers are built from electric switches that have two natural states : “off ” and “on”. </li></ul><ul><ul><li>“ off ” implies ‘0’ and “on” implies ‘1’. </li></ul></ul><ul><li>The internal language of computers comprises of group of bits such as 10010011 11011001. </li></ul><ul><li>To provide communication between a computer and human users ,a means of translating information between human and machine (binary) formats is necessary. </li></ul>
    9. 9. COMPUTER ORGANIZAION :- Is concerned with the way the hardware components operate and the way they are connected together to form the computer system. Components assumed to be in place and task is to investigate the organizational structure to verify that the computer parts operate as intended.
    10. 10. COMPUTER ARCHITECTURE :- Is concerned with the structure and the behavior of the computer as seen by the user. It includes the information formats, instruction set (IO, Data transfer), and techniques for addressing memory. The architectural design of a computer system is concerned with the specifications of the various functional modules such as processors and memories, and structuring them together into a computer system.
    11. 11. <ul><li>Evolution of Computers </li></ul><ul><li>Calculating machines capable of performing the elementary operations of arithmetic (Addition, subtraction, multiplication and division) appeared in 16 th century. </li></ul><ul><li>These were mechanical devices constructed from gears, levers etc. </li></ul><ul><li>After that, various attempts were made to build general-purpose programmable computers from the same mechanical devices. </li></ul>
    12. 12. <ul><li>A mechanical computer has two serious drawbacks: </li></ul><ul><li>Its computing speed is limited by the inertia of its moving parts. </li></ul><ul><li>The transmission of digital information is quite unreliable. </li></ul><ul><li>Now the development was the introduction of Electronic Computers in the mid-20 th century. </li></ul><ul><li>In an electronic computer the moving parts are electrons which can be transmitted and processed reliably. </li></ul><ul><li>First electronic computer was ENIAC (Electronic Numerical Integrator and Calculator) stored their programs and data in separate memories. </li></ul><ul><li>ENIAC had a set of electronic memory units called accumulators with a combined capacity of twenty 10-digit decimal numbers. </li></ul><ul><li>Entering or altering the programs was a tedious task. </li></ul>
    13. 13. <ul><li>STORED PROGRAM CONCEPT </li></ul><ul><li>Illustrates that the Idea of storing programs and data in same high-speed memory. </li></ul><ul><li>Next EDVAC (Electronic Discrete variable Computer ) – (Von Neumann Model) Stored program concept Besides facilitating the programming process, enables a program to modify its own instructions. </li></ul><ul><li>It Stored and processed numbers in true binary form. </li></ul><ul><li>It had two types of memory: fast main memory and slower secondary memory. </li></ul><ul><li>It had defined Instruction format: A1 A2 A3 A4 OP </li></ul><ul><li>To minimize hardware costs, data was processed serially, or bit by bit. </li></ul><ul><li>After that, A new stored-program electronic computer referred as IAS computer (Institute for Advanced Studies). </li></ul>
    14. 14. <ul><li>The General structure it had – </li></ul><ul><li>A CPU for executing instructions </li></ul><ul><li>A main memory for storing active programs </li></ul><ul><li>A secondary memory for backup storage </li></ul><ul><li>Miscellaneous Input-Output equipments. </li></ul><ul><li>The IAS machine processes all bits of a binary number simultaneously or in parallel. </li></ul><ul><li>Earliest Computers had their instructions written in a binary code known as machine language . </li></ul><ul><li>Improvement in machine language by allowing the operations and operand addresses to be expressed in symbolic format, referred to as assembly language . </li></ul>
    15. 15. <ul><li>IAS design have two key aspects: </li></ul><ul><li>CPU contains a small set of high-speed storage devices called registers which serves as implicit storage locations for operands and results. </li></ul><ul><li>A program’s instructions are stored in main memory in approximately the sequence in which they are executed. Hence, the address of the next instruction is usually that of the current instruction plus one. </li></ul><ul><li>One of the two main parts of CPU is responsible for fetching instructions from memory and interpreting them, this part is known as program control unit (PCU) or I-unit (instruction unit). </li></ul>
    16. 16. Instruction decoder …… . Control signals Program control unit (PCU) AR IR IBR PC DR Arithmetic- Logic unit AC MQ Data Processing unit DPU Address 0 1 2 3 4 4094 4095 M(2) M(1) M(0) M(3) M(4) M(4,094) M(4,095) Organization of CPU and main memory of IAS computer
    17. 17. <ul><li>The second major part of the CPU is responsible for executing instructions and is known as data processing unit , the datapath , or the E-unit (execution unit) . </li></ul><ul><li>PCU (Program Control Unit) </li></ul><ul><li>Major components of PCU are: </li></ul><ul><ul><li>Instruction register (IR) , which stores the opcode that is currently being executed. </li></ul></ul><ul><ul><li>Program counter (PC) which automatically stores and keeps track of the address of the next instruction to be fetched. </li></ul></ul>
    18. 18. <ul><li>PCU has circuits to interpret opcodes and to issue control signals to the DPU, main memory and other circuits involved in executing instructions. </li></ul><ul><li>PCU can modify the instruction execution sequence when required to do so by branch instructions. </li></ul><ul><li>PCU has 12-bit address register (AR) that holds the address of a data operand to be fetched from or sent to main memory. </li></ul><ul><li>IAS has feature of fetching two instructions at a time from main memory, it contains a second register, the instruction buffer register (IBR) ,for holding a second instruction. </li></ul>
    19. 19. <ul><li>DPU (Data Processing Unit) </li></ul><ul><li>Main components of DPU are the ALU , contains the circuits that perform addition, subtraction, multiplication etc. as required by opcodes. </li></ul><ul><li>DPU contains the Data registers (DR) to store data words temporarily during program execution. </li></ul><ul><li>IAS has two general-purpose 40-bit data registers : </li></ul><ul><ul><li>AC (Accumulator) </li></ul></ul><ul><ul><li>Data register (DR) </li></ul></ul><ul><li>DPU contains a Special-purpose data register MQ (Multiplier-quotient) intended for use by multiply and divide instructions. </li></ul>
    20. 20. <ul><li>IAS fetches, decodes and executes the instruction in several steps that form an instruction cycle . </li></ul><ul><li>IAS fetches two instructions in each instruction cycle. One instruction has its opcode placed in IR and its address field placed in AR. </li></ul><ul><li>The other instruction is transferred to IBR register for possible later execution. </li></ul><ul><li>Whenever the next instruction needed by the CPU is not in IBR, the program counter is incremented to generate the next instruction address. </li></ul><ul><li>As the desired instruction has been loaded into CPU its execution phase begins. </li></ul><ul><li>PCU decodes the instruction’s opcode. </li></ul>
    21. 21. <ul><li>The contents of the memory location specified by the address register AR are transferred to the data register DR. </li></ul><ul><li>Contents of DR and the accumulator AC are executed via the DPU’s arithmetic-logic unit and the result is placed in AC. </li></ul><ul><li>♣ PROGRAM COUNTER: </li></ul><ul><li>¤ There is 1 register in the computer called the program counter or PC that keeps track of the instructions in the program stored in memory. </li></ul><ul><li>¤ PC holds the address of the instructions to be executed next and is incremented each time an instruction is fetched from memory. </li></ul><ul><li>¤ The decoding of the instruction is done in the next step tells which operation is to be performed, the addressing mode of the instruction, and the location of the operands. </li></ul><ul><li>¤ The computer then executes the instruction and returns to the step1, i.e. to fetch the next instruction. </li></ul>
    22. 22. FLYNN’S CLASSIFICATION OF COMPUTERS A processor as CPU operates by fetching instructions and operands from memory executing the instructions and placing the final result in memory. The instructions from an instruction stream flowing from memory to processor while the operands from another stream data stream, flowing to and from the processor. The sequence of instructions read from memory constitutes an instruction stream. The operations performed on the data in the processor constitutes a data stream. Memory M Processor P Instruction Stream Stream Data
    23. 23. Flynn has proposed a broad classification based on the number of simultaneous instruction streams and data streams seen by the processor during program execution . SISD (Single Instruction Stream, Single data stream) SIMD (Single Instruction Stream, Multiple data stream) MISD (Multiple Instruction Stream, Single data stream) MIMD (Multiple Instruction Stream, Multiple data stream) SISD represents the organization of a single computer containing a CU, a processor unit & a memory unit. SIMD represents an organization that includes many processing units under the supervision of a common control unit. MIMD refers to a computer system capable of processing several programs at the same time.
    24. 24. Classification of processors based on Instruction set (J.P. Hayes 194) <ul><li>The primary objective of processor designer is to improve performance. </li></ul><ul><li>Performance is defined as the amount of work that the processor can do in a given period of time. </li></ul><ul><li>Different instructions perform different amount of work. </li></ul><ul><li>To increase performance ,either have the processor that execute many instructions in less time (inc. the clock speed of the processor) ,or make each instruction to execute more work (inc. the power & complexity of each instruction). </li></ul>
    25. 25. CISC & RISC <ul><li>CISC stands for COMPLEX INSTRUCTION SET COMPUTER. </li></ul><ul><li>RISC stand for REDUCE INSTRUCTION SET COMPUTER. </li></ul><ul><li>RISC is the generic name given to processors that use a small number of simple instructions, to try to do less work with each instruction but execute them much faster. </li></ul>
    26. 26. RISC INSTRUCTIONS <ul><li>RISC processor is restricted to the use of LOAD & STORE instructions when communicating b/w memory & CPU. </li></ul><ul><li>Most RISC instructions involve only register-to-register operations that are internal to CPU. </li></ul>
    27. 27. RISC CHARACTERISTICS <ul><li>SIMPLE INSTRUCTION SET :-The instruction set contains simple, basic instruction, from which more complex instructions can be composed. </li></ul><ul><li>SAME LENGTH INSTRUCTIONS :- Each instruction is of the same length, so that it may be fetched in a single operation. </li></ul><ul><li>1 MACHINE CYCLE INSTRUCTIONS :-Most instructions complete in one machine cycle, which allows the processor to handle several instructions at the same time. </li></ul>
    28. 28. ADVANTAGES <ul><li>SPEED :-RISC processors often achieve 2 to 4 times the performance of CISC processors. </li></ul><ul><li>SIMPLER HARDWARE :- it uses much less chip space; extra functions like memory management unit or floating point arithmetic unit, can also be placed on same chip. </li></ul><ul><li>Smaller chips allow a semiconductor mfg. to place more parts on a single silicon wafer, which can lower the per chip cost dramatically. </li></ul><ul><li>SHORTER DESIGN CYCLE :-RISC processors are simpler than corresponding CISC processors, they can be designed more quickly. </li></ul>
    29. 29. RISC HAZARDS <ul><li>CODE QUALITY :-The performance of RISC processor depends on the code that it is executing. If the programmer or compiler does a poor job of instruction scheduling, the processor can spend quite a bit of time waiting for the result of one instruction before it can proceed with a subsequent instruction. </li></ul><ul><li>DEBUGGING :- Instruction scheduling can make debugging difficult. </li></ul><ul><li>CODE EXPANSION :-CISC machines perform complex action with a single instruction, whereas RISC machines may require multiple instructions for the same action, code expansion can be a problem. </li></ul><ul><li>code expansion refer to the increase in size when the program is compiled for CISC machine & re-compiled for RISC machine. The exact expansion depend primarily on the quality of compiler and the nature of machine’s instruction set. </li></ul>
    30. 30. INSTRUCTION SET FORMATS (M.M. 255) <ul><li>A computer usually has a variety of Instruction Code Formats. It is the function of the control unit within the CPU to interpret each instruction code and provide the necessary control functions needed to process the instruction. </li></ul><ul><li>The bits of the instruction are divided into groups called fields. </li></ul><ul><li>The most common fields in instruction formats are: </li></ul><ul><li>An Operation code field that specifies the operation to be performed. </li></ul><ul><li>An Address field that designates a memory address or a processor register. </li></ul><ul><li>A Mode field that specifies the way the operand or the effective address is determined. </li></ul>Instruction format with mode field Address Mode Opcode
    31. 31. Types of Instruction Sets <ul><li>Data Transfer Instructions : Load, Store </li></ul><ul><li>Arithmetic Instructions: Add, Subtract </li></ul><ul><li>Logical Instructions: AND, OR </li></ul><ul><li>Program Control Instructions: Jump, Branch, Break </li></ul><ul><li>Input-Output Instructions: Instructions related to IO devices. e.g. Rewind, Print Line </li></ul>
    32. 32. <ul><li>Computers may have instructions of several different lengths containing varying number of addresses. </li></ul><ul><li>The number of address fields in the instruction format of a computer depends on the internal organization of its registers. </li></ul><ul><li>Most computers fall into one of 3 types of CPU organizations: </li></ul><ul><li>1. Single accumulator organization:- All the operations are performed with an accumulator register. The instruction format in this type of computer uses one address field. </li></ul><ul><li>For example: ADD X </li></ul><ul><li>where X is the address of the operands . </li></ul><ul><li>2. General register organization:- The instruction format in this type of computer needs three register address fields. </li></ul><ul><li>For example: ADD R1,R2,R3 </li></ul>
    33. 33. <ul><li>3. Stack organization </li></ul><ul><li>For example : ADD </li></ul><ul><li>The instruction in a stack computer consists of an operation code with no address field. This operation has the effect of popping the 2 top numbers from the stack, adding the numbers and pushing the sum into the stack. </li></ul><ul><li>To illustrate the influence of the number of address on computer programs, we will evaluate the arithmetic statement </li></ul><ul><li>X=(A+B)*(C+D) </li></ul><ul><li>Using Zero,one,two,or three address instructions. </li></ul>
    34. 34. <ul><li>Computers may have instructions of several different lengths containing varying number of addresses. </li></ul><ul><li>THREE-ADDRESS INSTRUCTIONS : </li></ul><ul><li>Computers with 3-address instruction formats can use each address field to specify either a processor register or a memory operand. </li></ul><ul><li>For example: ADD R1, A, B </li></ul><ul><li> ADD R2, C, D </li></ul><ul><li> MUL X, R1,R2 </li></ul><ul><li>ADVANTAGE: It results in short programs when evaluating arithmetic expressions. </li></ul><ul><li>DISADVANTAGE: The instructions requires too many bits to specify 3 addresses. </li></ul>
    35. 35. <ul><li>2. TWO-ADDRESS INSTRUCTIONS: </li></ul><ul><li>Two-address instructions are the most common in commercial computers. </li></ul><ul><li>Here again each address field can specify either a processor register, or a memory word. </li></ul><ul><li>For example: MOV R1,A </li></ul><ul><li> ADD R1,B </li></ul><ul><li> MOV R2,C </li></ul><ul><li> ADD R2,D </li></ul><ul><li> MUL R1,R2 </li></ul><ul><li> MOV X,R1 </li></ul><ul><li>The first symbol listed in an instruction is assumed to be both a source and the destination where the result of the operation is transformed. </li></ul>
    36. 36. <ul><li>3. ONE-ADDRESS INSTRUCTION: </li></ul><ul><li>One-address instruction use an implied accumulator (AC) register for all data manipulation. </li></ul><ul><li>For example: LOAD A </li></ul><ul><li>ADD B </li></ul><ul><li>STORE T </li></ul><ul><li>LOAD C </li></ul><ul><li>ADD D </li></ul><ul><li>MUL T </li></ul><ul><li>STORE X </li></ul><ul><li>All operations are done between the AC register and a memory operand. </li></ul>
    37. 37. <ul><li>4. ZERO-ADDRESS INSTRUCTIONS: </li></ul><ul><li>A stack-organized computer does not use an address field for the instructions. </li></ul><ul><li>The PUSH and POP instructions, need an address field to specify the operand that communicates with the stack. </li></ul><ul><li>For example: PUSH A </li></ul><ul><li> PUSH B </li></ul><ul><li>ADD </li></ul><ul><li> PUSH C </li></ul><ul><li>PUSH D </li></ul><ul><li> ADD </li></ul><ul><li> MUL </li></ul><ul><li> POP X </li></ul><ul><li>To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into reverse polish notation. </li></ul><ul><li>The name “zero-address” is given to this type of computer because of the absence of an address field in the computational instructions. </li></ul><ul><li>--------------------------------------------------------------------- </li></ul>
    38. 38. <ul><li>THE ADDRESSING MODES: (M.M. Chapter -8) </li></ul><ul><li>Specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually referenced. </li></ul><ul><li>computers use addressing mode techniques for the purpose of accommodating the following purposes:- </li></ul><ul><li>1.) To give programming versatility to the user by providing such facilities as pointers to memory, counters for loop control, indexing of data and various other purposes. </li></ul><ul><li>2.) To reduce the number of bits in the addressing field of the instructions. </li></ul><ul><li>Other computers use a single binary for operation & Address mode. </li></ul><ul><li>The mode field is used to locate the operand . </li></ul><ul><li>Address field may designate a memory address or a processor register. </li></ul><ul><li>There are 2 modes that need no address field at all ( Implied & immediate modes ). </li></ul>
    39. 39. <ul><li>The most well known addressing mode then are: </li></ul><ul><li>Implied mode. </li></ul><ul><li>Immediate mode </li></ul><ul><li>Register mode </li></ul><ul><li>Register Indirect mode </li></ul><ul><li>Auto-increment or Auto-decrement mode </li></ul><ul><li>Direct Mode </li></ul><ul><li>Indirect Mode </li></ul><ul><li>Relative Address Mode </li></ul><ul><li>Index Addressing Mode </li></ul>
    40. 40. <ul><li>Although most addressing modes modify the address field of the instruction, there are two modes that need no address field at all: </li></ul><ul><li>1.) Implied mode </li></ul><ul><li>2.) Immediate mode. </li></ul><ul><li>IMPLIED MODE: </li></ul><ul><li>In this mode the operands are specified implicitly in the definition of the instruction. </li></ul><ul><li>For example:- </li></ul><ul><li>“ complement accumulator” is an implied-mode instruction because the operand in the accumulator register is implied in the definition of the instruction. In fact, all register reference instructions that use an accumulator are implied-mode instructions. </li></ul>
    41. 41. <ul><li>Immediate mode: </li></ul><ul><li>In this mode the operand is specified in the instruction itself. In other words, an immediate-mode instruction has an operand field rather than an address field. </li></ul><ul><li>The operand field contains the actual operand to be used in conjunction with the operation specified in the instruction. </li></ul><ul><li>It was mentioned previously that the address field of an instruction may specify either a memory word or a processor register. When the address field specifies a processor register, the instruction is said to be in register-mode. </li></ul>
    42. 42. <ul><li>Register direct mode: </li></ul><ul><li>In this mode the operands are in registers that reside within the C.P.U. </li></ul><ul><li>The particular register is selected from the register field in the instruction. </li></ul><ul><li>A K-bit field can specify any one of 2 k registers. </li></ul><ul><li>Register indirect mode: </li></ul><ul><li>In this mode the instruction specifies a register in the CPU whose contents give the address of the operand in the memory. </li></ul><ul><li>In other words, the selected register contains the address of the operand rather than the operand itself. </li></ul><ul><li>Before using a register indirect mode instruction, the programmer must ensure that the memory address of the operand is placed in the processor register with a previous instruction. </li></ul><ul><li>Advantage: </li></ul><ul><li>The address field of the instruction uses fewer bits to select a register than would have been required to specify a memory address directly. </li></ul>
    43. 43. <ul><li>Auto increment or Auto decrement : </li></ul><ul><li>This is similar to register indirect mode except that the register is incremented or decremented after (or before) its value is used to access memory. </li></ul><ul><li>When the address stored in the registers refers to a table of data in memory, it is necessary to increment or decrement the registers after every access to the table. </li></ul><ul><li>This can be achieved by using the increment or decrement instruction. In some computers it is automatically accessed. </li></ul><ul><li>The address field of an instruction is used by the control unit in the CPU to obtain the operands from memory. </li></ul><ul><li>Sometimes the value given in the address field is the address of the operand, but sometimes it is the address from which the address has to be calculated. </li></ul><ul><li>For that we need to know about the concept of ‘EFFECTIVE ADDRESS’. </li></ul>
    44. 44. <ul><li>Effective address: </li></ul><ul><li>The effective address is defined to be the memory address obtained from the computation dictated by the given addressing mode. </li></ul><ul><li>The effective address is the address of the operand in a computational-type instruction. </li></ul><ul><li>DIRECT ADDRESS MODE:- </li></ul><ul><li>In this mode the effective address is equal to the address part of the instruction. The operand resides in memory and its address is given directly by the address field of the instruction . </li></ul>
    45. 45. INDIRECT ADDRESS MODE <ul><li>In this mode the address field of the instruction gives the address where the effective address is stored in memory. </li></ul><ul><li>Control unit fetches the instruction from the memory and uses its address part to access memory again to read the effective address. </li></ul><ul><li>Some addressing modes requires the following to calculate the effective address: </li></ul><ul><li>Effective address= address part of instruction+ </li></ul><ul><li>content of CPU register </li></ul>
    46. 46. Central Processing Unit Addressing modes Indirect Mode Effective Address of the operand is the contents of a register or a memory location whose address appears in the instruction. R1 Add (R1),R0 Add (A),R0 Register B B Operand memory Main A B Operand B <ul><li>Register R1 contains Address B </li></ul><ul><li>Address B has the operand </li></ul><ul><li>Address A contains Address B </li></ul><ul><li>Address B has the operand </li></ul>R1 and A are called “pointers”
    47. 47. RELATIVE ADDRESS MODE <ul><li>In this mode the content of the program counter is added to the address part of the instruction in order to obtain the effective address. </li></ul><ul><li>The address part of the instruction is usually a signed number(either a +ve or a –ve number). </li></ul><ul><li>When the number is added to the content of the program counter, the result produces an effective address whose position in memory is relative to the address of the next instruction. </li></ul>
    48. 48. INDEXED ADDERESSING MODE <ul><li>In this mode the content of an index register is added to the address part of the instruction to obtain the effective address. </li></ul><ul><li>The index register is a special CPU register that contains an index value. </li></ul><ul><li>NOTE: </li></ul><ul><li>If an index-type instruction does not include an address field in its format, the instruction is automatically converted to the register indirect mode of operation. </li></ul>
    49. 49. BASE REGISTER ADDRESSING MODE <ul><li>In this mode the content of a base register is added to the address part of the instruction to obtain the effective address. </li></ul><ul><li>This is similar to the indexed addressing mode except that the register is now called a base register instead of the index register. </li></ul><ul><li>The base register addressing mode is used in computers to facilitate the relocation of programs in memory. </li></ul><ul><li>When programs and data are moved from one segment of memory to another. </li></ul>
    50. 50. Central Processing Unit Addressing modes Numerical Example (M.M. 265) : Two word instruction at 200&201 Address=500 Next Instruction 450 700 800 900 325 300 Load to AC Mode Memory 500 Address 201 202 399 400 702 600 200 800 PC=200 R1=400 XR=100 AC Addressing mode eff. Add Content of AC ----------------------------------------------------------- Direct Address 500 800 Immediate operand 201 500 Indirect Address 800 300 Relative Address 702 (PC=PC+2) 325 Indexed Address 600 (XR+500) 900 Register --- 400 Register Indirect 400 700 Auto-increment 400 700 Auto-decrement 399 450 Tabular list
    51. 51. TYPES OF INTERRUPT <ul><li>In a computer, having interrupt facility, when the input / output device is ready for the data transfer, it sends an interrupt signal to the computer </li></ul><ul><li>In the mean time, the computer may be busy with other tasks. </li></ul><ul><li>After receiving the interrupt signal, the computer fulfills the request of I/O device. </li></ul><ul><li>The interrupt enable flip-flop IEN can be set and cleared with 2 instructions (ION and IOF). When IEN is cleared to 0, the flags can not interrupt the computer. When IEN is set to 1, the computer can be interrupted. </li></ul><ul><li>These 2 instructions provide the programmer with the capability of making a decision as to whether or not to use the interrupt facility. </li></ul>
    52. 52. <ul><li>TYPES OF INTERRUPTS: 3 major types are: </li></ul><ul><li>External interrupts </li></ul><ul><li>Internal interrupts </li></ul><ul><li>Software interrupts </li></ul><ul><li>External interrupts come from I/O devices, from a timing device, from a circuit monitoring the power supply, or from any other external source. For example: Timeout interrupt </li></ul><ul><li>Internal interrupts arise from illegal or erroneous use of an instruction or data. Internal interrupts are also called traps . For example, attempt to divide by zero. </li></ul>
    53. 53. <ul><li>The difference between internal interrupt and external interrupt is that the internal interrupt is initiated by some exceptional condition caused by program itself rather than by an external event. External interrupts depend on external conditions that are independent of the program. </li></ul><ul><li>SOFTWARE INTERRUPT: A software interrupt is initiated by executing an instruction. Software interrupt is a special call instruction that behaves like an interrupt rather than a subroutine call. The most common use of a software interrupt is associated with a supervisor call instruction. This instruction provides means for switching from a CPU user mode to the supervisor mode. </li></ul>
    54. 54. PROGRAMMED I/O, DMA & INTERRUPTS <ul><li>These all are modes of transfer. </li></ul><ul><li>Data transfer between the central computer and the I/O devices may be handled in a variety of modes. </li></ul><ul><li>The modes are: </li></ul><ul><li>Programmed I/O. </li></ul><ul><li>Interrupt-initiated I/O </li></ul><ul><li>Direct memory access (DMA) </li></ul>

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