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2.computer org.

  1. 1. Unit – 4 Computer Organization Ch- 5 & 7 Morris Mano
  2. 2. Instruction Codes <ul><li>The organization of the computer is defined by its internal registers, the timing and control structure, and the set of instructions that it uses. </li></ul><ul><li>The internal organization of a digital system is defined by the sequence of micro-operations it performs on data stored in its registers. </li></ul><ul><li>The user can control the process by means of a program. </li></ul><ul><li>A program is a set of instructions that specify the operations, operands & the sequence by which processing has to occur. </li></ul><ul><li>A computer instruction is a binary code that specifies a sequence of microoperations for the computer. </li></ul><ul><li>Every computer has its own instruction set. </li></ul><ul><li>Instruction codes together with data are stored in memory. </li></ul><ul><li>The computer reads each instruction from memory and places it in a control register. </li></ul><ul><li>The control then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of micro-operations. </li></ul><ul><li>An instruction code is a group of bits that instructs the computer to perform a specific operation. </li></ul>
  3. 3. <ul><li>It is usually divided into parts, each having its own interpretation. </li></ul><ul><li>The most basic part of an instruction code is its operation part. </li></ul><ul><li>For every operation code, the control issues a sequence of micro-operations needed for the hardware implementation of the specified operation. </li></ul><ul><li>An instruction code must specify not only the operation but also the registers or the memory words where the result is to be stored. </li></ul><ul><li>Memory words can be specified in instruction codes by their address. </li></ul>
  4. 4. <ul><li>Stored Program Organization : </li></ul><ul><li>The simplest way to organize a computer is to have one processor register and an instruction code format with 2 parts. The first part specifies the operation to be performed and the second part specifies an address. </li></ul><ul><li>Computers that have a single processor register usually assign to it the name accumulator and label it AC. </li></ul>
  5. 5. Stored program Organization (Fig 5.1) Opcode Address Binary Operand Instructions (Program) Operands (data) Memory 4096 x 16 Instruction format Processor register (AC) 15 12 11 0 15 0
  6. 6. Computer Registers (Fig 5-4 M.M.) <ul><li>The computer needs processor registers for manipulating data and a register for holding a memory address. </li></ul><ul><li>List of Registers </li></ul><ul><li>1. DR DATA REGISTER </li></ul><ul><li>2. AR ADDRESS REGISTER </li></ul><ul><li>3. AC ACCUMULATOR </li></ul><ul><li>4. IR INSTRUCTION REGISTER </li></ul><ul><li>5. PC PROGRAM COUNTER </li></ul><ul><li>6. TR TEMPORARY REGISTER </li></ul><ul><li>7. INPR INPUT REGISTER </li></ul><ul><li>8. OUTR OUTPUT REGISTER </li></ul>
  7. 7. <ul><li>The AR and PC register has 12 bits since this is the width of a memory address. </li></ul><ul><li>The DR holds the operand read from memory. </li></ul><ul><li>The AC register is a general-purpose processing register. </li></ul><ul><li>The instruction read from memory are placed in the IR. </li></ul><ul><li>The TR is used for holding temporary data during processing. </li></ul><ul><li>Two registers INPR and OUTR are used for input and output device and these are of 8 bits. </li></ul>
  8. 8. <ul><li>COMMON BUS SYSTEM (Fig 5.4) </li></ul><ul><li>The basic computer has 8 registers, a memory unit and a control unit. </li></ul><ul><li>Paths must be provided to transfer information from one register to another and between memory and registers. </li></ul><ul><li>The no. of wires will be excessive if connections are made between the output of each register and the inputs of other registers. </li></ul><ul><li>A more efficient scheme for transferring information in a system with many registers is to use a common bus. </li></ul>
  9. 9. COMPUTER INSTRUCTIONS <ul><li>INSTRUCTION FORMAT : The basic computer has 3 instruction code formats. </li></ul><ul><li>Each format has 16 bits. </li></ul><ul><li>The operation code (opcode) part of the instruction contains 3 bits and the meaning of the remaining 13 bits depends on the operation code encountered. </li></ul><ul><li>A memory-reference instruction uses 12 bits to specify an address and one bit to specify the addressing mode I. </li></ul><ul><li>I is equal to 0 for direct address and 1 for indirect address. </li></ul><ul><li>The register-reference instruction does not need operand from memory ; therefore 12 bits are used to specify the operation to be executed. </li></ul><ul><li>Register-reference instructions are recognized by opcode 111 and 0 in the leftmost bit. </li></ul><ul><li>Input-output reference instructions are recognized by opcode 111 and 1 in the leftmost bit. The remaining 12 bits are used to specify the type of input-output operation. </li></ul>
  10. 10. Basic Computer Instruction formats (Table 5.2) I Opcode Address 0 1 1 1 Register operation 1 1 1 1 I/O operation 15 14 12 11 0 15 12 11 0 15 14 12 11 0
  11. 11. <ul><li>INSTRUCTION SET COMPLETENESS </li></ul><ul><li>The set of instructions are said to be complete if the computer includes a sufficient number of instructions in each of the following categories: </li></ul><ul><li>Arithmetic, logical and shift instructions </li></ul><ul><li>Instructions for moving information to and from memory and processor registers </li></ul><ul><li>Program control instructions together with instructions that check status conditions </li></ul><ul><li>Input and output instructions </li></ul>
  12. 12. TIMING AND CONTROL (Sec 5.4) <ul><li>The timing for all registers in the basic computer is controlled by a master clock generator. </li></ul><ul><li>The clock pulses are applied to all flip-flops and registers in the system, including the flip-flops and registers in the control unit. </li></ul><ul><li>The clock pulses do not change the state of a register unless the register is enabled by a control signal. </li></ul><ul><li>The control signals are generated in the control unit. </li></ul>
  13. 13. <ul><li>2 TYPES OF CONTROL ORGANIZATIONS: </li></ul><ul><li>Hardwired control </li></ul><ul><li>Microprogrammed control </li></ul><ul><li>Hardwired control : In this the control logic is implemented with gates, flip-flops, decoders and other digital circuits. </li></ul><ul><li>Advantage: Can be optimized to produce a fast mode of operation. </li></ul><ul><li>Microprogrammed Control : In the microprogrammed organization, the control information is stored in a control memory. </li></ul><ul><li>The control memory is programmed to initiate the required sequence of microoperations. </li></ul><ul><li>Any updation can be easily done by updating the microprogram in control memory. </li></ul>
  14. 14. <ul><li>Control Unit of Basic Computer (Fig 5.6) </li></ul><ul><li>It consists of 2 decoders, a sequence counter and a number of control logic gates. </li></ul><ul><li>An instruction read from memory is placed in the IR where it is divided into 3 parts: the I bit, opcode and bits 0 through 11. </li></ul><ul><li>The 4 bit sequence counter can count in binary from 0 through 15. </li></ul><ul><li>The outputs of the counter are decoded into 16 timing signals T 0 Through T 15 . </li></ul>
  15. 15. Accumulator Logic (Sec-5.10) <ul><li>Refer fig 5-19 </li></ul><ul><li>The adder and logic circuit has 3 sets of inputs. </li></ul><ul><li>One set of 16 inputs comes from the output of AC. </li></ul><ul><li>Another set of 16 inputs comes from DR. </li></ul><ul><li>A third set of 8 inputs comes from the input register INPR. </li></ul><ul><li>The output of the adder and logic circuit provide the data inputs for the register. </li></ul><ul><li>In addition, it is necessary to include logic gates for controlling the LD, INR and CLR inputs for controlling the operation of the adder and logic circuit. </li></ul>
  16. 16. <ul><li>CONTROL OF AC REGISTER: </li></ul><ul><li>Refer the figure 5-20 </li></ul><ul><li>The gate structure controls the LD,INR and CLR inputs of AC . </li></ul><ul><li>The output of the gate that generates the control function for the clear micro-operation is connected to the CLR input of the register . </li></ul><ul><li>Similarly, the output of the gate that implements the increment micro-operation is connected to the INR input of the register. </li></ul><ul><li>The other 7 micro-operations are generated in the adder and logic circuit and are loaded into AC at the proper time. </li></ul><ul><li>These outputs are used in the design of the adder and logic circuit. </li></ul>
  17. 17. <ul><li>Adder and Logic Circuit: The adder and logic circuit can be subdivided into 16 stages, with each stage corresponding to 1 bit of AC. </li></ul><ul><li>Each stage has a JK flip-flop and 2 AND gates. </li></ul><ul><li>One stage of the adder and logic circuit consists of 7 AND gates, one OR gate and a full-adder (FA). </li></ul><ul><li>The AND operation is achieved by ANDing AC(i) with the corresponding bit in the date register DR(i). </li></ul><ul><li>The ADD operation is obtained using a binary adder . </li></ul><ul><li>The complement micro-operation is obtained by inverting the bit value in AC. </li></ul><ul><li>The complete adder and logic circuit consists of 16 stages connected together. </li></ul>
  18. 18. CONTROL MEMORY (Chapter 7 M.M.) <ul><li>The function of the control unit is to initiate sequences of micro-operations. </li></ul><ul><li>The control function that specifies a micro-operation is a binary variable. </li></ul><ul><li>When it is in one binary state, the corresponding micro-operations is executed. A control variable in the opposite binary state does not change the state of the registers in the system. </li></ul><ul><li>A control unit whose binary variables are stored in memory is called a microprogrammed control unit. </li></ul><ul><li>Each word in control memory contains within it a micro-instruction. </li></ul><ul><li>The micro-instruction specifies one or more micro-operations for the system. </li></ul><ul><li>Since alterations of the micro-program are not needed once the control unit is on operation, the control memory can be a read-only memory (ROM). </li></ul>
  19. 19. <ul><li>A more advanced development known as dynamic micro-programming permits a micro-program to be loaded initially from an auxiliary memory such as a magnetic disk. </li></ul><ul><li>A memory that is a part of control unit is referred to as a control memory . </li></ul><ul><li>A computer that employs a micro-programmed control unit will have 2 separate memories: A main memory and a control memory. </li></ul><ul><li>The control memory holds a fixed micro-program that cannot be altered by the occasional user. </li></ul><ul><li>The micro-instructions generate the micro-operations to fetch the instruction from memory. </li></ul>
  20. 20. <ul><li>Refer the figure –7.1 </li></ul><ul><li>The control memory is assumed to be a ROM, within which all control information is permanently stored. </li></ul><ul><li>The control address register specifies the address of the micro-instruction. </li></ul><ul><li>The control data register holds the micro-instruction read from memory. </li></ul><ul><li>The next address generator is called a micro-program sequencer, as it determines the address sequence that is read from control memory. </li></ul><ul><li>The main advantage of microprogrammed control is the fact that once the hardware configuration is established, there should be no need for further hardware or wiring changes. </li></ul><ul><li>If we want to establish a different control sequence for the system, all we need to do is specifying a different set of micro-instructions for the control memory. </li></ul>
  21. 21. Address Sequencing (Chapter 7 M.M.) <ul><li>Micro-instructions are stored in control memory in groups, with each group specifying a routine. </li></ul><ul><li>Each instruction has its own micro-program routine in control memory to generate the micro-operations that execute the instruction. </li></ul><ul><li>The hardware must be capable of sequencing the micro-instructions within a routine and be able to branch from one routine to another. </li></ul><ul><li>Steps for Address Sequencing: </li></ul><ul><li>An initial address is loaded into the control address register when power is turned on in the computer. </li></ul><ul><li>The fetch routine may be sequenced by incrementing the control address register through the rest of micro-instructions. </li></ul><ul><li>The control memory next must go through the routine that determines the effective address of the operand. </li></ul><ul><li>The effective address computation routine in control memory can be reached through a branch micro-instruction. </li></ul>
  22. 22. <ul><li>When the effective address computation routine is completed, the address of the operand is available in the memory address register. </li></ul><ul><li>The next step is to generate the micro-operations that execute the instruction fetched from memory. </li></ul><ul><li>The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process. </li></ul><ul><li>A mapping procedure is a rule that transforms the instruction code into a control memory address. </li></ul><ul><li>After the required routine is reached, the micro-instructions that execute the instruction may be sequenced by incrementing the control address register. </li></ul><ul><li>The address sequencing capabilities required in a control memory are: </li></ul><ul><li>Incrementing of the control address register. </li></ul><ul><li>Unconditional branch or conditional branch, depending on status bit conditions. </li></ul><ul><li>A mapping process from the bits of the instruction to an address for control memory. </li></ul><ul><li>A facility for subroutine call and return. </li></ul>
  23. 23. <ul><li>Refer the figure-7.2 </li></ul><ul><li>The micro-instruction in control memory contains a set of bits to initiate micro-operations in computer registers and other bits to specify the method by which the next address is obtained. </li></ul><ul><li>There are 4 different paths from which the Control Address Register (CAR) receives the address. </li></ul><ul><li>The incrementer increments the content of the control address register by one, to select the next microinstruction in sequence. </li></ul><ul><li>Branching is achieved by specifying the branch address in one of the fields of the micro-instruction. </li></ul><ul><li>Conditional branching is obtained by using part of the micro-instruction to select a specific status bit in order to determine its condition. </li></ul><ul><li>The return address for a subroutine is stored in a special register whose value is then used when the micro-program wishes to return from the subroutine. </li></ul>
  24. 24. <ul><li>Mapping Of Instruction: A special type of branch exists when a micro-instruction specifies a branch to the first word in control memory where a micro-program routine for an instruction is located. </li></ul><ul><li>The status bits for this type of branch are the bits in the operation code part of the instruction. </li></ul><ul><li>The mapping function is sometimes implemented by means of an integrated circuit called programmable logic device or PLD. A PLD is similar to ROM in concept except that it uses AND and OR gates with internal electronic fuses. </li></ul><ul><li>Subroutines: Subroutines are programs that are used by other routines to accomplish a particular task. </li></ul><ul><li>A subroutine can be called from any point within the main body of the micro program. </li></ul><ul><li>Micro-instructions can be saved by employing subroutines that use common sections of micro-code. </li></ul><ul><li>For example, the sequence of micro-operations needed to generate the effective address of the operand for an instruction is common to all memory-reference instructions . </li></ul>
  25. 25. MICRO-INSTRUCTION FORMAT (Chapter 7 M.M.) <ul><li>Refer the figure 7.6 </li></ul><ul><li>The 20 bits of the micro-instruction are divided into 4 functional parts. </li></ul><ul><li>The 3 fields F1,F2 AND F3 specify micro-operations for the computer. </li></ul><ul><li>The CD field selects status bit conditions. </li></ul><ul><li>The BR field specifies the type of branch to be used. </li></ul><ul><li>The AD field contains a branch address. The address field is 7 bits wide, since the control memory has 128=2 7 words. </li></ul><ul><li>The micro-operations are subdivided into 3 fields of 3 bits each. </li></ul><ul><li>The 3 bits in each field are enclosed to specify 7 distinct micro-operations. This gives a total of 21 microoperations. </li></ul><ul><li>No more than 3 microoperations can be chosen for a micro-instruction, one from each field. </li></ul><ul><li>If fewer than 3 microoperations are to be used, one or more of the fields will use the binary code 000 for no operation. </li></ul>
  26. 26. <ul><li>The CD (condition) field consists of 2 bits which are encoded to specify 4 status bit conditions. </li></ul><ul><li>The BR(BRANCH) field consists of 2 bits. It is used in conjunction with the address field AD, to choose the address of the next micro-instruction. It can be jump, call, return. </li></ul><ul><li>SYMBOLIC MICRO-INSTRUCTION: A symbolic micro-program can be translated into its binary equivalent by means of an assembler. </li></ul><ul><li>The simplest way to formulate an assembly language for a micro-program is to define symbols for each field of the micro-instruction and to give users the capability for defining their own symbolic addresses. </li></ul><ul><li>Each micro-instruction is divided into 5 fields: Label, microoperations, CD, BR and AD. </li></ul>
  27. 27. <ul><li>The fields specify the following information: </li></ul><ul><li>The label field may be empty or it may specify a symbolic addresses. A label is terminated with a colon (:). </li></ul><ul><li>The microoperations field consists of one, two or three symbols, separated by commas. </li></ul><ul><li>The CD field has one letter like U (Unconditional branch). </li></ul><ul><li>The BR field contains one symbol. </li></ul><ul><li>The AD field specifies a value for the address field of the micro-instruction. </li></ul>
  28. 28. Instruction Cycle <ul><li>A program residing in the memory unit of the computer consists of a sequence of instructions. </li></ul><ul><li>The program is executed in the computer by going through a cycle for each instruction. </li></ul><ul><li>Each instruction cycle is subdivided into a sequence of phases. </li></ul><ul><li>In the basic computer each instruction cycle consists of the following phases: </li></ul><ul><li>Fetch an instruction from memory. </li></ul><ul><li>Decode the instruction. </li></ul><ul><li>Read the effective address from memory if the instruction has an indirect address. </li></ul><ul><li>Execute the instruction. </li></ul><ul><li>(Note (very Important) : Fig 5-9 Flow Chart for Instruction Cycle) </li></ul>
  29. 29. <ul><li>Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the next instruction. </li></ul><ul><li>Fetch and Decode </li></ul><ul><li>Initially, the program counter PC is loaded with the address of the first instruction in the program. </li></ul><ul><li>The sequence counter SC is cleared to 0, providing a decoded timing signal T 0 . </li></ul><ul><li>After each clock pulse, SC is incremented by one, so that the timing signals go through a sequence T 0 , T 1 , T 2 and so on. </li></ul>
  30. 30. <ul><li>The micro-operations for the fetch and decode phases can be specified by the following register transfer statements. </li></ul><ul><li>T O : AR PC </li></ul><ul><li>T 1 : IR M[AR], PC PC + 1 </li></ul><ul><li>T 2 : D 0 ,….., D 7 Decode IR(12-14). </li></ul><ul><li>AR IR(0-11), I IR(15) </li></ul><ul><li>Since only AR is connected to the address inputs of memory, it is necessary to transfer the address from PC to AR during the clock translation associated with timing signal T 0. </li></ul><ul><li>The instruction read from memory is then placed in the instruction register IR with the clock transition associated with timing signal T 1 . </li></ul>
  31. 31. <ul><li>At the same time, PC is incremented by one to prepare it for the address of the next instruction in the program. </li></ul><ul><li>At time T 2 , the operation code in IR is decoded, the indirect bit is transferred to flip-flop I, and the address part of the instruction is transferred to AR. </li></ul><ul><li>Note that SC is incremented after each clock pulse to produce the sequence T 0 , T 1 and T 2 . </li></ul><ul><li>Refer to figure 5-8. </li></ul>
  32. 32. <ul><li>To provide the data path for the transfer of PC to AR we must apply timing signal T 0 to achieve the following connection: </li></ul><ul><li>Place the content of PC onto the bus by making the bus selection inputs S 2 S 1 S 0 equal to 010. </li></ul><ul><li>Transfer the content of the bus to AR by enabling the LD inputs of AR. </li></ul><ul><li>It is necessary to use timing signal T 1 to provide the following connections in the bus systems. </li></ul><ul><li>Enable the read input of memory. </li></ul><ul><li>Place the content of memory onto the bus by making S 2 S 1 S 0 =111. </li></ul><ul><li>Transfer the content of the bus to IR by enabling the LD input of PC. </li></ul><ul><li>Increment PC by enabling the INR input of PC. </li></ul>
  33. 33. <ul><li>Types of instructions: </li></ul><ul><li>Memory-Reference Instructions </li></ul><ul><li>Register-Reference Instructions </li></ul><ul><li>Input-Output Instructions </li></ul><ul><li>The Total no. of instructions chosen for the basic computer is equal to 25. </li></ul>
  34. 34. Determine the Type of Instruction <ul><li>The timing signal that is active after the decoding is T 3 . </li></ul><ul><li>During time T 3 , the control unit determines the type of instruction that was just read from memory. </li></ul><ul><li>Register-Reference Instructions </li></ul><ul><li>Register-reference instructions are recognized by the control when D 7 = 1 and I = 0. </li></ul><ul><li>These instructions use bits 0 through 11 of the instruction code to specify one of 12 instructions. </li></ul><ul><li>These instructions are executed with the clock transition associated with timing variable T 3 . </li></ul><ul><li>Each control function needs the Boolean relation D 7 I’T 3 , which we designate for convenience by the symbol r. </li></ul><ul><li>The control function is distinguished by one of the bits in IR(0-11). We assign the symbol B i to bit i of IR. </li></ul>
  35. 35. <ul><li>The execution of the Register-reference instruction is completed at time T 3 . </li></ul><ul><li>The sequence counter SC is cleared to 0 and the control goes back to fetch the next instruction with timing signal T 0 . </li></ul><ul><li>The register-reference instructions are following: </li></ul><ul><li>CLA rB 11 Clear AC </li></ul><ul><li>CLE rB 10 Clear E </li></ul><ul><li>CMA rB 9 Complement AC </li></ul><ul><li>CME rB 8 Complement E </li></ul><ul><li>CIR rB 7 Circulate right </li></ul><ul><li>CIL rB 6 Circulate left </li></ul><ul><li>INC rB 5 Increment AC </li></ul><ul><li>SPA rB 4 Skip if positive </li></ul><ul><li>SNA rB 3 Skip if negative </li></ul><ul><li>SZA rB 2 Skip if AC zero </li></ul><ul><li>SZE rB 1 Skip if E zero </li></ul><ul><li>HLT rB 0 Halt computer </li></ul>
  36. 36. 2. Memory-Reference Instructions <ul><li>These are recognized by the control when D 7 =0. </li></ul><ul><li>When D 7 = 0 and I= 1, then it is Indirect memory-reference instruction. </li></ul><ul><li>When D 7 = 0 and I = 0, then it is direct memory-reference instruction. </li></ul><ul><li>The effective address of the instruction is in the address register AR and was placed there during timing signal T 2 when I = 0, or during timing signal T 3 when I = 1. </li></ul><ul><li>The execution of the memory-reference instruction starts with timing signal T 4 . </li></ul><ul><li>The actual execution of the instruction in the bus system will require a sequence of micro-operations. </li></ul><ul><li>This is because data stored in memory can not be processed directly. </li></ul><ul><li>The data must be read from memory to a register where they can be operated on logic circuits. </li></ul>
  37. 37. <ul><li>Memory-reference instructions are: </li></ul><ul><li>Symbol Operation Symbolic </li></ul><ul><li>decoder description </li></ul><ul><li>---------------------------------------------------------------- </li></ul><ul><li>AND D0 AC AC ^ M[AR] </li></ul><ul><li>ADD D1 AC AC + M[AR] </li></ul><ul><li>LDA D2 AC M[AR] </li></ul><ul><li>STA D3 M[AR] AC </li></ul><ul><li>BUN D4 PC AR </li></ul><ul><li>BSA D5 M[AR] PC, PC AR + 1 </li></ul><ul><li>ISZ D6 M[AR] M[AR] + 1, </li></ul><ul><li> If M[AR] + 1=0 THEN PC PC + 1 </li></ul>
  38. 38. 3. Input-Output Instructions <ul><li>A computer can serve no useful purpose unless it communicates with the external environment. </li></ul><ul><li>Instructions and data stored in memory must come from some input device. </li></ul><ul><li>Computational results must be transmitted to the user through some output device. </li></ul><ul><li>Input-Output Configuration: The terminal sends and receives serial information. </li></ul><ul><li>Each quantity of information has eight bits of an alphanumeric code. </li></ul><ul><li>The serial information from the keyboard is shifted into the input register INPR. </li></ul><ul><li>The serial information for the printer is stored in the output register OUTR. </li></ul><ul><li>These 2 registers communicate with a communication interface serially and with the AC in parallel. </li></ul><ul><li>Refer figure 5-12 </li></ul>
  39. 39. <ul><li>The transmitter interface receives serial information from the keyboard and transmits it to INPR. </li></ul><ul><li>The receiver interface receives information from OUTR and sends it to the printer serially. </li></ul><ul><li>The 1-bit input flag FGI is a control flip-flop. </li></ul><ul><li>The flag bit is set to 1 when new information is available in the input device and is cleared to 0 when the information is accepted by the computer. </li></ul><ul><li>The flag is needed to synchronize the timing rate difference between the input device and the computer. </li></ul><ul><li>The output register OUTR works similarly but the direction of information flow is reversed. </li></ul>
  40. 40. <ul><li>Input-Output Instructions are needed for transferring information to and from AC register, for checking the flag bits and for controlling the interrupt facility. </li></ul><ul><li>Input-output Instructions are: </li></ul><ul><li>SC:- 0 Clear SC </li></ul><ul><li>INP AC(0-7):- INPR, FGI:- 0 Input character </li></ul><ul><li>OUT OUTR:-AC(0-7), FGO:- 0 Output character </li></ul><ul><li>SKI If(FGI =1) then (PC:- PC+1) Skip on Input flag </li></ul><ul><li>SKO If(FGO =1) then (PC:- PC+1) Skip on output flag </li></ul><ul><li>ION IEN:-1 Interrupt enable on </li></ul><ul><li>IOF IEN:-0 Interrupt enable off </li></ul><ul><li>------------------------------------------------------------------------------- </li></ul>
  41. 41. Microprogram Sequencer (Chapter 7 M.M.) <ul><li>The basic components of a micro-programmed control unit are the control memory and the circuits that selects the next address. </li></ul><ul><li>The address selection part is called a micro-program sequencer. </li></ul><ul><li>A micro-program sequencer can be constructed with digital functions to suit a particular application. </li></ul><ul><li>The purpose of a micro-program sequencer is to present an address to the control memory so that a micro-instruction can be read and executed. </li></ul>
  42. 42. <ul><li>The next address logic of the sequencer determines the specific address source to be loaded into the control address register. </li></ul><ul><li>The choice of the address source is guided by the next-address information bits that the sequencer receives from the present micro-instruction. </li></ul><ul><li>Refer the figure… </li></ul><ul><li>There are 2 multiplexers in the circuit. </li></ul><ul><li>The first multiplexer selects an address from one of 4 sources and routes it into a Control Address Register (CAR). </li></ul><ul><li>The second multiplexer tests the value of a selected status bit and the result of the test is applied to an input logic circuit. </li></ul><ul><li>The output from CAR provides the address for the control memory. </li></ul>
  43. 43. <ul><li>The content of CAR is incremented and applied to one of the multiplexer inputs and to the subroutine register SBR. </li></ul><ul><li>The CD field of the micro-instruction selects one of the status bits in the multiplexer. </li></ul><ul><li>If the bit selected is equal to 1, the T (test) variable is equal to 1; otherwise it is equal to 0. </li></ul><ul><li>The T value together with the two bits from the BR (branch) field go to an input logic circuit. </li></ul><ul><li>The input logic in a particular sequencer will determine the type of operations that are available in the unit. </li></ul>
  44. 44. <ul><li>The typical sequencer operations are: increment, branch or jump, call and return from subroutine, load an external address, push or pop the stack and other address sequencing operations. </li></ul><ul><li>With 3 inputs, the sequencer can provide up to 8 address sequencing operations. </li></ul><ul><li>The input logic circuit has 3 inputs, I 0 ,I 1 and T and 3 outputs, S 0 ,S 1 and L. </li></ul><ul><li>Variables S 0 and S 1 select one of the source addresses for CAR. </li></ul><ul><li>Variable L enables the load input in SBR. </li></ul><ul><li>The binary values of the 2 selection variables determine the path in the multiplexer. For example, with S 1 S 0 = 10, multiplexer input number 2 is selected and establishes a transfer path from SBR to CAR. </li></ul>
  45. 45. Stack Organization <ul><li>A stack is a storage device that stores the information in such a manner that the item stored last is the first item received. </li></ul><ul><li>The register that holds the address for the stack is called a stack pointer (SP) because its value always points at the top item of the stack. </li></ul><ul><li>The 2 operations of stack are PUSH (for insertion) and POP (For deletion). </li></ul>
  46. 46. <ul><li>REGISTER STACK: A stack can be placed in a portion of a large memory or it can be organized as a collection of a finite number of memory words or registers. </li></ul><ul><li>For example, in a 64-word stack, the SP contains 6 bits because 2 6 =64. </li></ul><ul><li>There are 2 one-bit registers FULL and EMTY. If stack is full, then FULL is set to 1. </li></ul><ul><li>When the stack is empty of item, EMTY is set to 1. </li></ul><ul><li>DR is the data register that holds the binary data to be written or read out of the stack. </li></ul>
  47. 47. <ul><li>MEMORY STACK : A stack can be implemented in RAM attached to the CPU. </li></ul><ul><li>The implementation of a stack in the CPU is done by assigning a portion of memory to a stack operation and using a processor register as a stack pointer. </li></ul><ul><li>S tack limits: Most computers do not provide hardware to check overflow ( full stack ) or underflow (empty stack). The stack limits can be checked by using two processors registers: </li></ul><ul><li>One to hold the upper limit and the other to hold the lower limit. </li></ul><ul><li>After a push operation, SP is compared with the upper-limit register and after a pop operation, SP is compared with the lower-limit register. </li></ul>
  48. 48. <ul><li>A stack organization is very effective for evaluating arithmetic expressions. </li></ul><ul><li>The common arithmetic expressions are written in infix notation, with each operator written between the operands, but it causes some difficulties when expression is evaluated by the computer. </li></ul><ul><li>For example, A * B + C * D </li></ul><ul><li>So, we can use Prefix notation or Postfix notation. </li></ul>