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IEEE CASE 2011, Italy - Conference Paper Presentation
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IEEE CASE 2011, Italy - Conference Paper Presentation

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Paper presented by Prof. Zhou, NJIT and co-authored by Ashish Ratnakar

Paper presented by Prof. Zhou, NJIT and co-authored by Ashish Ratnakar

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IEEE CASE 2011, Italy - Conference Paper Presentation IEEE CASE 2011, Italy - Conference Paper Presentation Presentation Transcript

  • An Ultrasound System for TumorDetection in Soft Tissues using LowTransient PulseMengChu Zhou, Fellow, IEEEAshish Ratnakar, Member, IEEE
  • Introduction• Research paper mainly concentrates on breast tumors• Breast cancer – leading cause of cancer deaths in women worldwide• National Breast Cancer Coalition 2009 Statistics – Of 254,650 new cases, 192,370 were invasive• Expert’s Suggestion – Detect it early, cure it early!!• Research paper presents the design and implementation of an ultrasound imaging technology based on FPGA/DSP co-design architecture for detection and determination of tumor location and size• Many other detection technologies studied and compared
  • Previous Research• X-Ray Mammography – Early stage cancer detection, high false-positives (up to 70%) and high false-negatives (4 – 34%) for patients with radiographically dense tissues , also unsafe for women under 40• Magnetic Resonance Imaging (MRI) – more sensitive than X- Ray, Higher rate of false positives• Ultrasound Imaging is non-invasive/non-ionizing tool• Quantitative Ultrasound (QUS) – advantages in terms of cost, size, safety and detection resolution• Low Transient Pulse (LTP) – compress acoustic pulse to improve imaging resolution
  • Ultrasound Imaging and LTP• Non-Destructive Testing (NDT) technology• Ultrasonic waves emitted into an object reflect back if there is an impurity or crack• Echo analyzed for different parameters• LTP utilizes similar technique – Short duration pulse echoes out high frequency signal when it comes across any impurity• LTP drive signal can be synthesized using high speed logic gate arrays which cause less phase interference and leads to better performance
  • Low Transient Pulse• Produces short duration, low transient acoustic pulseby means of pre-shaping transmitter excitation• Less phase Peak A1+ A2 can be eliminated when interference pulse width is equated to difference• Improves signal between pulse arrival time detection resolution
  • Why FPGA/DSP Co-Design• Accelerates execution speed of task that could have done on DSP alone – Unloads DSP from least important tasks• FPGA has disadvantages of increasing complexity and overhead. Hence can’t be done on FPGA alone• FPGA – High frequency computations• DSP – Data Processing• A task partitioned between DSP and FPGA according to speed and functionality requirement• In this design, DSP – Center of the system – processes data at 1MHz Detection of tumor size and location FPGA – performs high frequency tasks at 62.5MHz Generation of LTP drive, QAM demodulation
  • Experimental Setup• TMS320C64xx based DSP Starter Kit• Xilinx Spartan IIE FPGA based DSK Daughter card• A set of Ultrasonic Transducer• X-Y Robot
  • DSP and FPGA Considerations• TMS320C6416T DSP Performance up to 8000 MIPS at 1GHz Programmed through Code Composer Studio (CCS) Better Speed/Cost ratio than other competitive DSPs• Xilinx Spartan IIE XC2S300E FPGA Code generated using Xilinx ISE Programmed through Code Composer Studio Versatility of fast programmable solution
  • Ultrasound Systems• Ultrasound frequencies – cyclic sound pressure frequencies with lower limit 20 KHz• Reflection signature in a medium reveals the inner details of medium• Inexpensive and portable than MRI and CT• Safe when used at diagnostic power level• Application in wide areas like medical imaging, cleaning of metals, tracking and identification of objects
  • Analysis of the System• Study of ultrasound properties of tumors• Preparation of simulated tumors’ samples with similar properties• Assessment and comparison of samples with non-tumor samples and with each other• Implementation of analysis on FPGA/DSP co-design• Testing of implementation for the results
  • Ultrasonic Properties ofTumors• Benign Fluid-filled Non-carcinogenic Echolucent• Malignant Solid Carcinogenic Echogenic/ Echolucent
  • Method of Analysis of Samples• Analysis done in a way to imitate B- mode ultrasound• Transmitter kept at fixed position while receiver position is varied to fixed angles of 25°, 45°, 90°, 135° and 180°
  • Analysis of Plain Sample• Determination of velocity of ultrasound in sample gel• Necessary for standardization while calculating and determining location of tumor while taking delay into account in case of echolucent and echogenic sample• Velocity of ultrasound can be calculated as v=d/t where d – distance travelled through medium when Tx and Rx are at 180° apart t – time taken by the signal to arrive from Tx to Rx
  • Analysis of Echogenic PhantomSample• The ratio of calculated values to computed values for 90° and 135° is approx. 1.3• First peak in case of (a) is nearly equal to reflected path from the tumor which strongly indicates presence of echogenic sample
  • Analysis of Echolucent Sample• The ratio of calculated values to computed values for 90° and 135° is approx. 1.4• Case (a) shows coupling between transmitter and receiver and hence, can be ignored
  • System Implementation• Co-design Environment Programming • Architecture first designed, examined and optimized with high level simulation of complete system • Different sub-blocks translated into Matlab/Simulink model • Validation of corresponding VHDL programs done with simulator and experimental outputs are verified • Algorithm developed to determine tumor location from demodulated data from DSP memory • System designed and implemented on DSP with calibration for noise removal
  • System Implementation - DSP• Center of FPGA/DSP architecture• Detection of location and size of tumor• Controls various aspects of system like initialization of ADC and FPGA, system timer and FPGA/DSP interface• TMS320C6416T Key Features 1GHz, 8000MIPS high performance fixed-point processor 2 external memory interfaces: 64-bit EMIFA and 16-bit EMIFB 3 general purpose 32-bit timers• Memory Mapping Each EMIF has 4 addressable chip-enable spaces (CE0-CE3) This EMIF uses CE2 of EMIFA for communication with on-board daughter-card components
  • System Implementation – DSP(contd.)• Timers Timer_1 signals external ADC, DAC and FPGA on daughter-card Runs at 62.5MHz as DSP uses CPU Clock/8 as internal clock Clock is further divided for ADC (1MHz with Timer_0) and other modules using clock divider in FPGA• Interrupts DSP has 16 prioritized interrupts with INT00 to INT03 non-masked INT04 – implemented to indicate completion of task assigned to ADC on the daughter-card Assembly file used to configure interrupts through CCS
  • System Implementation - DSP(contd.)• FPGA Configuration A function loads configuration data into FPGA through ‘C’ program running on DSP DSP starts writing from address VIRTEX_MEM to address pointed by VIRTEX_ADDR• ADC Configuration Configured to select internal reference voltage with continuous conversion mode and output is set in binary mode• DSP Execution Flow Interrupts cleared and re-enabled  EMIFA CE2 space control register configured for communication between DSP and daughter-card  DAC1 and DAC2 addresses initialized  Timer_0 set to count 32 cycles  ADC initialized with INT04 for Timer_1
  • System Implementation – DSP(contd.)• High Freq Noise filtering INT04 ISR implemented with Simple Moving Avg. Filtering with window size ‘16’• Locating Tumor Filtered data passed through max1 max2 algorithm to detect first two peaks of the envelope
  • System Implementation - FPGA• QAM Demodulator • Required to receive baseband signal from HF modulated carrier signal • Removes noise • Carrier frequency = 150KHz • Filter cut-off = 75KHz • Signals are squared and added before calculating square-root to obtain the envelope LTP drive, Rx output and envelope
  • System Implementation –FPGA (Contd.)• Programming the FPGA – done using Xilinx ISE with VHDL• MSI approach used • Functions are divided into adders, multipliers and flip-flops • Each function written in VHDL and simulated in ModelSim simulator • Different blocks created together to form larger blocks. e.g. Sine wave generator and square-root generator • These functional blocks port-mapped to form large blocks. e.g. QAM
  • System Implementation –FPGA (Contd.)• Generation of LTP • FPGA configured as 12-bit module preloaded with the corresponding binary value of each pulse to drive DAC • Values output through circular buffer correspond to 2.6V and 1.6V for dual voltage LTP at DAC1 output • Pulse-width = 3.75µS • LTP drive frequency = 400Hz RTL for LTP Generation
  • System Implementation –FPGA (Contd.)• Clock Divider • Different modules run at different clock speeds • Implemented to generate LTP and run DAC1 at high frequency while ADC and other modules at relatively lower frequency • Lower clock frequency 1MHz is achieved by setting clock count as 31 RTL for Clock Divider
  • System Implementation –FPGA (Contd.)• FPGA and DSP interface • Shared memory locations between FPGA and DSP in EMIFA • DSP requests data on EMIFA from ADC • After receiving data, DSP processes it as well as writes processes data into DAC • Data has to be processed within 1µS as ADC interrupts every 1µS Interface between FPGA and DSP
  • System Implementation –FPGA (Contd.)• QAM Demodulator Components • Sine and Cosine Carrier Generator - Circular buffer with fixed values derived from Matlab implemented for both waves at 150KHz, sampled at 1MHz - Output values from buffer are repetitive after 20 samples Matlab simulation of Sine Wave RTL of Carrier Generator
  • System Implementation –FPGA (Contd.)• QAM Demodulator Components • Square Root Generator - Implemented using ‘Restoring Binary Shift-and-Subtract Square Rooting’ algorithm - In an input vector of length 2n, algorithm calculates the square root of length n - Subtractor subtracts expression P(i) from successive remainder R(i-1) and final result is the concatenation of sign bits of Q. P(i) = (4×Q(n-i) +1)×22(n-i) • IIR Filter - 2nd Order Direct - II form Butterworth LPF implemented due to low gate count - Phase delays can be ignored as filter implemented in forward loop - Filter Gain = 0.041253, Sampling Freq = 1MHz, Cut-off Freq = 75KHz
  • System Implementation –FPGA (Contd.)• QAM Demodulator – Frequency Spectrum Analysis - 150KHz received signal sampled at 1MHz - Algorithm on DSP is too complex to finish in 1µS. Hence, received signal can’t be sent to DSP without QAM demodulation - QAM demodulation shifts frequency spectrum towards zero giving DSP sufficient time to finish execution of algorithm Freq. Spectrum Without QAM Shifted Freq. Spectrum With QAM
  • System Implementation –FPGA (Contd.)• FPGA Component Interconnections • ADC sends sampled data to QAM Demodulator for detection of baseband signal • Detected signal  DSP • DSP  Moving average filtering and peak detection • Filtered data  DAC2 • LTP Synthesized  DAC1 Mapping of FPGA Interconnections
  • Experimental Results • Calculation of velocity of ultrasound in Plain Sample • V = 12.1cm / 99µS = 1222.22 m/s • Experiments on Echogenic Sample • Precise distances of echogenic mass from 0°, 25°, 45°, 90°, 135° and 180° are 3.5, 3.7, 3.5, 4.6, 5.6 and 5.2cmAngle ΔT1(µS) ΔT2(µS) L1(cm) L2(cm) Lc(cm) ε(cm)25° 60 62 7.33 7.58 3.67 0.0345° 78 117 9.53 14.3 5.86 2.3690° 88 92 10.76 11.24 4.97 -0.37135° 99 120 12.09 14.66 5.63 0.03180° 98 126 11.98 15.4 11.98 0.32 Lc – Corrected Length ε – Error between actual length and Lc 180° case indicates distance between Tx and Rx with delay Possibility of prediction of size, shape and location of tumor
  • Experimental Results • Experiments on Echolucent Sample • Precise distances of echogenic mass from 0°, 25°, 45°, 90°, 135° and 180° are 2.6, 3, 3, 4.6, 5.3 and 5.4cmAngle ΔT1(µS) ΔT2(µS) L1(cm) L2(cm) L1c(cm)25° 33 179 4.03 21.87 2.0245° 99 102 12.09 12.47 12.0290° 87 139 10.63 16.99 7.59135° 99 121 12.09 14.79 8.64180° 99 120 12.09 14.67 12.09 - Absence of maximum between ΔT1 and ΔT2 for 25° case concludes that either there is no tumor or the tumor, if exists, is echolucent - Possible to predict existence of echolucent tumor but hard to locate
  • Conclusions• LTP drive signal  comparatively easy prediction of nature and location of tumor• FPGA/DSP Platform  Efficient way to implement synthesis of drive and detection of location, nature and size of tumor• Further Analysis of tumors that are echogenic as well as echolucent in nature like Pancreatic Cystadenocarcinoma is required• False-positives and false-negatives  to be analyzed• Once calibrated for transducers and false-results, design can be implemented into a handy device that helps medical practitioners to carry out primary analysis instead of using expensive techniques like CT and MRI
  • Thank You!!