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Traffic Lights Logic Controller
 

Traffic Lights Logic Controller

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Traffic Lights Logic Controller ...

Traffic Lights Logic Controller

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The project we have chosen is an 8-lane traffic controller. The basic idea behind the design is to avoid the collision of vehicles by providing appropriate signals to different directions for a limited time slot, after which the next waiting drivers will be given same treatment. In This way a cycle will be established which will control the traffic.

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    Traffic Lights Logic Controller Traffic Lights Logic Controller Document Transcript

    • INTRODUCTION Traffic signals are used to control the flow of vehicles.In the recent years, the need of transportation has gain immense importance for logistics as well as for common human. This has given rise to the number of vehicles on the road. Due to this reason, traffic jams and road accidents are a common sight in any busy city. Traffic Signals provide an easy, cheap, automatic and justified solution to the road points where the vehicles may turn to other directions e.g. roundabouts, culverts, busy walk throughs etc. BASIC IDEA The project we have chosen is an 8-lane traffic controller. The basic idea behind the design is to avoid the collision of vehicles by providing appropriate signals to different directions for a limited time slot, after which the next waiting drivers will be given same treatment. In This way a cycle will be established which will control the traffic. CONTROL SIGNALS The control signals are 3-lights.  Top light is Red(Stop),  Middle light is Yellow(Wait)  Bottom light is Green(Go). STATES OF TRAFFIC FLOW There are 8-lanes and at most two ways can be safely open. In this way a minimum of 4-states are possible for which different vehicles will pass through. These four states according to direction are : 1. North-South South-North 2. South-East North-West 3. East-West West-East 4. East-North West-South STATE DIAGRAM Page # 1
    • These states are shown graphically below: State --- 1 State State ---2 State ---3 Page # 2
    • GENERAL FLOW OF CIRCUIT 1. Timer 2. Counter 3. Decoder 4. Output Logic Page # 3
    • TIMER In our project we used 555 Timer IC as the Timer or Pulse Generator. 555 IC INTRODUCTION The 555 timer IC is an amazingly simple yet versatile device. It has been around now for many years and has been reworked into a number of different technologies. The two primary versions today are the original bipolar design and the more recent CMOS equivalent. These differences primarily affect the amount of power they require and their maximum frequency of operation. The 555 Timer is a TTL digital logic circuit that is used in the controller circuit to produce a periodic square wave signal. The period and duty cycle of the square wave signal are determined by the resistors and capacitors connected to the timer. APPLICATIONS  Precision timing  Pulse generation  Sequential timing  Time delay generation  Pulse width modulation  Pulse position modulation  Linear ramp generator Page # 4
    • FUNCTIONAL BLOCK DIAGRAM The figure to the right shows the functional block diagram of the 555 timer IC. The IC is available in either an 8-pin round TO3-style can or an 8-pin mini-DIP package. In either case, the pin connections are as follows: 1. Ground. 2. Trigger input. 3. Output. 4. Reset input. 5. Control voltage. 6. Threshhold input. 7. Discharge. 8. +VCC. +5 to +15 volts in normal use. Page # 5
    • PIN CONNECTIONS OPERATION The operation of the 555 timer revolves around the three resistors that form a voltage divider across the power supply, and the two comparators connected to this voltage divider. The IC is quiescent so long as the trigger input (pin 2) remains at +VCC and the threshhold input (pin 6) is at ground. Assume the reset input (pin 4) is also at +VCC and therefore inactive, and that the control voltage input (pin 5) is unconnected. Under these conditions, the output (pin 3) is at ground and the discharge transistor (pin 7) is turned on, thus grounding whatever is connected to this pin. WORKING FORMULAE Page # 6
    • The frequency, or repetition rate, of the output pulses is determined by the values of two resistors, R1 and R2 and by the timing capacitor, C. The HIGH and LOW times of each pulse can be calculated from: Before calculating a frequency, one should know that it is usual to make R1=1 kW because this helps to give the output pulses a duty cycle close to 50%, that is, the HIGH and LOW times of the pulses are approximately equal. PARAMETERS CALCULATION In this project we want to design a circuit to produce a frequency of approximately 0.25 Hz( 4 sec ) for generating clock pulse. What values of R1, R2 and C should we use? R1 should be 1kΩ, as already explained. This leaves you with the task of selecting values for R2 and C. The best thing to do is to rearrange the design formula so that the R values are on the right hand side: Here we choose the value of C as 1µF and R1 is selected as 1kΩ. Therefore the value of R2 is found as: 1 + 2R2 = ( 1.44 ) / ( f * C ) 1 + 2R2 = ( 1.44 ) / ( 0.25 * 1µ) R2 = 2.8 MΩ Page # 7
    • Hence the circuit parameters for timer are: Vcc = 5 V R1 = 1 kΩ . R2 = 2.8 MΩ . C = 1µF TIMER WIRING DIAGRAM Page # 8
    • COUNTER INTRODUCTION In this project we need a 5-bit synchronous binary up-counter. Since such a 5-bit counter is not available in packaged form so we have to design it using basic gates and flip flops. SYNCHRONOUS COUNTERS A synchronous counter is one whose output bits change state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flip-flops is to connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time. We know that we still have to maintain the same divide-by-two frequency pattern in order to count in a binary sequence, and that this pattern is best achieved utilizing the "toggle" mode of the flip-flop, so the fact that the J and K inputs must both be (at times) "high" is clear. A general structure of a counter is shown below: The red question marks are indicating that there some other connections will be made in order to complete the whole counter. To determine the gates required at each flip-flop input, let's draw up a truth table for all states of the counter. Page # 9
    • TRUTH TABLE Present State Next State Flip Flop Inputs A B C D E A B C D E TA TB TC TD TE 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 1 0 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 1 1 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 1 1 0 1 1 0 0 0 0 1 1 1 0 1 1 0 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 Page # 10
    • K-MAP MINIMIZATION For TA TA CDE 000 001 011 010 110 111 101 100 AB 0 1 3 2 6 7 5 4 00 01 8 9 11 10 14 15 1 13 12 24 25 27 26 30 30 29 28 11 1 16 17 19 18 22 23 21 20 10 TA = BCDE For TB TB CDE 000 001 011 010 110 111 101 100 AB 0 1 3 2 6 7 5 4 00 1 01 8 9 11 10 14 15 1 13 12 24 25 27 26 30 30 29 28 11 1 10 16 17 19 18 22 23 1 21 20 TB = CDE For TC Page # 11
    • TC CDE 000 001 011 010 110 111 101 100 AB 0 1 3 2 6 7 5 4 00 1 1 01 8 9 11 1 10 14 15 1 13 12 24 25 27 26 30 30 29 28 11 1 1 10 16 17 19 1 18 22 23 1 21 20 TC = DE For TD TD CDE 000 001 011 010 110 111 101 100 AB 0 1 3 2 6 7 5 4 00 1 1 1 1 01 8 9 1 11 1 10 14 15 1 13 1 12 24 25 27 26 30 30 29 28 11 1 1 1 1 10 16 17 1 19 1 18 22 23 1 21 1 20 TD = E For TE Since all the inputs of TE are 1 (High) therefore it’s output expression must be 1. TE = 1 COUNTER WIRING DIAGRAM Page # 12
    • Page # 13
    • S TAT E D E C O D E R INTRODUCTION: Here we use a demultiplexer as a state decoder to detect the counts of the 5-bit counter.For the decoding of 5-bit counter we have to use the 5 to 32 line decoder. This decoder is not available in the packaged form so we have to cascade two 4 to 16 line decoders. In this case we use the I.C 74154 which is a 24-pin package. DECODER WIRING DIAGRAM The interconnections for the decoder is shown below: : Page # 14
    • OUTPUT LIGHTING LOGIC INTRODUCTION The output lights will turn On and Off according to the logic designed for the flow of traffic for a particular time slot. There are a total of 24- Lights needed for 8-ways, and there are a maximum of 4- states( each having 3-lights i.e. red,yellow and green ) of flow.In this way we need to control only 12-lights and the other 12 are the raplica of the previous,so they can be connected in parallel. PRACTICAL TRAFFIC LIGHT TIMINGS In order to determine that for how long the red, yellow and green lights are ON and for how much time they are OFF, we carried out a survey of traffic signals installed at different locations including Hassan Square, Water Pump Roundabout, Nipa and Gulshan-e-Iqbal Roundabout.As a conclusion we found the following timings: LIGHTS RED YELLOW GREEN ON OFF ON OFF ON OFF 1 minute and 2 minutes 1 minute and 30 second 2 second 30 second 45 second 15 seconds 45 second The timings above are for one complete cycle of counts. We have tried our level best to design our circuit according to these timings. Page # 15
    • TRUTH TABLE Counts State 1 State 2 State 3 State 4 G G C1 C2 C3 C4 C5 G1 Y1 R1 Y2 R2 G3 Y3 R3 Y4 R4 2 4 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 Page # 16
    • Page # 17
    • WIRING DIAGRAM FOR RED LIGHTS: WIRING DIAGRAM FOR YELLOW LIGHTS: Page # 18
    • WORKING DIAGRAM FOR GREEN LIGHTS : Page # 19
    • OVERALL PIN DIAGRAM : Page # 20
    • B O M ( B I L L O F M AT E R I A L S ) Item Quantity Reference Part 1 1 C1 1µ 2 1 C2 0.01µ 3 1 RA 1k 4 1 RB 2.82M 5 1 SW1 SW MAG-SPDT 6 1 U LM555 7 2 U1,U2 74154 8 7 U1,U2,U14,U16,U17,U18,U19 7432 9 3 U4,U5,U15 7404 10 5 U6,U7,U10,U11,U12 7476 11 1 U13 7408 Page # 21
    • Page # 22
    • L I M I TAT I O N S Page # 23