As Resume 2011 12 07 00 54


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Resume for Dipl.-Ing. Andreas Schmidt (MSEE)

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As Resume 2011 12 07 00 54

  1. 1. Resume for Dipl.-Ing. Andreas Schmidt Personal Dipl.-Ing. Andreas Schmidt (MSEE) Oakland, CA, USA Mobile phone: +1-408-768-1088 em@il: homesite: Objective (Field-) Application / Technical Marketing / Product Management / Systems / ASIC / FPGA / IP Engineer / Manager in an innovative, industry-leading company Summary • Experience with VHDL/Verilog - synthesis /simulation /ASIC design tools since 1994 • Gate level simulation experience since 1992 • Experience with XILINX FPGA technology and tools since 1989 • Mixed-signal circuit and system design experience since 1984 • Experience with high speed serial connections (SerDes links) for inter-chip communication since 1991 • Used distributed parallel processing technology since 1991 • Double Data Rate (DDR) design experience since 1992 • Computer / system / network administrator experience since 1983 (UNIX, Windows) • Pro-audio engineering, sound reinforcement, and music technology experience since 1986 Special • Written highly portable, parameterized, modular, and scalable code in Verilog and VHDL for efficient portability, reusability, technology migration, and maintenance skills & • ASIC to FPGA, FPGA to ASIC, and IP migration experience highlights • Strong team building, facilitation, and mentoring skills • Worked effective with cross functional international teams and bridged gaps when needed • German engineering education and precision together with strong work ethics • Diligent project management, analytical problem solving, and facilitative leadership skills • Dual citizenship, multi-lingual • International working, presenter/trainer, and conference experience Experience Oct 2010 - present: ASIC.CC, Oakland, CA, USA Founder / Principal Engineer / Independent Contractor • Contractor at PRAESUM COMMUNICATIONS: • Installed and configured ALDEC Riviera-PRO (32bit & 64bit) running under FEDORA Linux • Migrated complex verification environments from Mentor ModelSim SE to ALDEC Riviera-PRO: • Constraint randomized self checking test environments using System Verilog, PLI/VPI, C++ • Serial RapidIO 2.1 Endpoint IP Core • Serial RapidIO I/O Logical Layer Initiator Core • Serial RapidIO I/O Logical Layer Target Core • PCIE Core • Serial RapidIO Switching IP Core • Different embedded processors • Supported Serial Rapid IO 2.1 Endpoint IP Core migration between different SerDes architectures (XILINX, ALTERA) • Optimized SerDes parameter settings for different implementations • Reviewed targeted designs and source code • Debugged implemented IP on evaluation boards in the lab • Supported technical marketing and product managementVersion: 2011. Copyright 1999-2011 for structure, layout, and content by Andreas Schmidt (ASIC.CC) Page 1 of 4
  2. 2. Experience 2005 – Sep 2010: XILINX, San Jose, CA, USA Staff Serdes Applications Engineer • Authored, edited, managed Virtex-5 GTP transceiver user guide [UG196] creation (SerDes on Virtex-5 LXT & SXT devices) • Authored, edited, managed Virtex-5 GTX transceiver user guide [UG198] creation (SerDes on Virtex-5 FXT & TXT devices) • Authored, edited, managed Virtex-6 GTX transceiver user guide [UG366] creation (SerDes on Virtex-6 LXT & SXT devices) • Authored, edited, managed Spartan-6 GTP transceiver user guide [UG386] creation (SerDes on Spartan-6 LXT devices) • Authored, edited, managed 7 Series FPGAs Transceivers User Guide [UG476] creation (SerDes on 7 Series FPGAs) • Provided worldwide SerDes trainings to SystemIO specialists and Field Application Engineers (FAE) • Supported key customers worldwide via escalation, implementation assistance, and on-site support • Board, signal & power integrity analysis, and system design reviews, root cause analysis • Reviewed designs of SerDes mixed-signal building blocks and provided feedback to IC-design 2004 – 2005: CloudShield Technologies, Sunnyvale, CA, USA Senior Design Engineer • Specified, designed, implementated, simulated, debugged, managed multiple FPGA (Xilinx Virtex II Pro/ ProX) designs for their flagship Network Packet Processing / Network security product CS2000 • Shipped successfully the designs as part of the first General Public Availability Release (Gigabit Ethernet, PCI (32bit/66MHz), bus interface to Intel IXP 2800 NPU, I2C, SONET OC48 framer, SPI 4.2 & SPI3 interfaces, inter-chip communication using Xilinx Rocket-IO transceiver (SerDes) on board level and on system level via backplane, SONET OC48 Overhead processing (at line rate with low latency), dynamic re-configuration of FPGAs via software) • Written testbenches / implementation code using Verilog2001 and simulation/implementation scripts • Facilitated and supported CVS (version control system) use inside the hardware group • Written automatic lab test environment for board bring-up using PERL (RedHat Enterprise Linux 3.0) • Debugged and corrected successfully third party code (Verilog) with insufficient and contradicting documentation available • Board bring-up and lab debugging in close interaction with firmware and board designers • CAD/EDA tool support, license administration / configuration, and consulting • Used ModelSim SE, Synplify Pro, Mentor Precision Synthesis, Xilinx ISE tool flow, Synopsys VirSim/ VCS, HyperLynx, and HSPICE tools 2001 – 2004: GIBSON Labs Technology Group, Sunnyvale, CA, USA (a Research and Development Division of GIBSON Guitar, Nashville, TN, USA) Senior ASIC Engineer • Architected, designed, simulated, implemented, managed the digital part of a mixed signal ASIC, which implemented the GIBSON MaGIC protocol in hardware (packet processing of real-time audio/video data on the MAC layer and above (100 MBit full duplex), interfacing to 24bit codecs for professional audio/ video applications (studio/concert/broadcast mixing hardware) • Developed generic design library and IP of the MaGIC transfer protocol • Consulted, trained team members in-house on ASIC/semiconductor technology • CAD/EDA tool support, license administration, system administration, and support • Written daily report to the CEO of GIBSON GUITAR Henry Juszkiewicz • Optimized an array of six magnetic micro transducers (Output amplitude, SNR, frequency response, chan- nel separation, crosstalk) using Finite Element Method Magnetics (FEMM) and SPICE ( the hexagonal magnetic pickup for the award-winning GIBSON MaGIC digital guitar) • Represented, evangelized, demonstrated MaGIC technology at the AES, CES, Frankfurter Musikmesse, Intel Developer Forum, NAMM show, and for music industry celebretiesVersion: 2011. Copyright 1999-2011 for structure, layout, and content by Andreas Schmidt (ASIC.CC) Page 2 of 4
  3. 3. Experience 2000 – 2001: Blue Iguana Networks (Nuvation spin-off), Fremont, CA, USA / Nuvation Labs Corporation, San Jose, CA, USA Senior Hardware Engineer • Concepted, specified, architected, implemented, managed the BI Logic engine core in VHDL (packet pro- cessing at the MAC layer and above at 100Mbit full-duplex) • Architected, developed, managed BI system technology on the target side (remote administration/reconfig- uration of FPGAs and systems via a validated, encrypted WAN connection with local fallback) • Definition, Technical Marketing of future BI technology (patent contribution/co-authoring, roadmap) Technical Lead • Designed, simulated, managed, integrated a Voice-over-IP design in Verilog (bidirectional 100Mbit Ether- net to T1/E1 bridge) for an optical network device (ONS for Alloptic) • Designed, simulated, managed, released a real-time video data processing and compression design for a jet flight display in VHDL (interface via TAXI SerDes) • Mentoring, team leading, in-house training, and consulting • CAD/EDA tool support, license administration, system administration, and support 1994 – 2000: Andreas Schmidt ASIC-Design, Technical Consulting, Hard- & Software, Bochum, Germany Entrepreneur / Consultant • Project work concerning digital circuit/system-design (using Xilinx Foundation, ALDEC Active-HDL, Synopsys, Synplicity, Mentor tools, Protel PCB, etc.), (VHDL, Verilog, mixed) • Architected, developed, sold computer solutions for specialized environments (medical technology) • Dealership authorizations: SUN-VAR, Apple-, Microsoft-, Microsoft education-dealer • Provided quality and efficiency management for the whole design process • Performed system administration of heterogeneous networks (SUN / Apple / WinNT - platforms) • Conducted technical consulting concerning networking, computer solutions, system design 1992 – 1996: Institute Electron Devices and Integrated Circuits, Ruhr-Universität Bochum, Germany Assistant to System administrator (1 year) • Administrated workstations running SunOS 4.1.3, Solaris 2.4, ULTRIX, Linux, MicroVMS • Programmed under SunOS, Solaris, ULTRIX • Installed, configured, administrated IC design development systems (Cadence, Synopsys, XILINX, etc.) Teaching Assistant: VLSI IC-design II design course (practical lab digital circuits) (3 years) • Developed course material, reviewed student designs, • Trained MSEE students on VLSI ICdesign techniques, tools, and methodologies using: •Xilinx FPGAs, Xilinx XACT, Synopsys tools, SunOS 4.1.3, SUN SPARC 10/20 •Mietec CMOS standardcells(1.2µ), Cadence Edge IC-design tools, ULTRIX, DECstation5000 •MMI CMOS gate arrays, Silvar-Lisco SL2000, MicroVMS, MicroVAXII 1991 – 1994: NEUROTECH GmbH, Oberhausen, Germany Developer of Digital circuits/systems • Designed interfaces to Hell/Linotype/Heidelberg repro graphic scanner/recorder • Used INMOS Transputer and XILINX FPGA technology (XC3090, XC4010, XACT), DATA-I/O Dash FutureNet, ViewLogic Workview • Designed system for real-time pre-press data processing using SerDes links, distributed parallel processors • Managed the project of the schematic-converter Dash2View (DataIO Dash -> ViewlogicWorkview) • Developed test programs using Pascal and OccamVersion: 2011. Copyright 1999-2011 for structure, layout, and content by Andreas Schmidt (ASIC.CC) Page 3 of 4
  4. 4. Education Ruhr-Universität Bochum, Germany: Dipl.-Ing. Elektrotechnik 1999/2000 (MSEE degree) Master-Thesis: „Realization of an efficient acquisition of measurement-data and control of a halfbridge-current-inverter for the operation of a Superconducting Magnetic Energy Storage system“ Education continuation: • Project Management (PM) classes at the San Jose State University as part-time student in order to reinforce my project management skills and to optimize them for the US (100% personally funded) • Employer funded classes and courses: •PLL analysis & design (US Santa Cruz extension) •High speed Noise & Grounding (Dr. Howard Johnson) •Managing At XILINX (MAX) •Managing Time and Multiple Priorities (Effective Training Associates) •Managing within the Law I&II •Breaktrough Project Management (Effective Training Associates) •Presenting for Action (Boyers Communication Group) •Writing for Action (Boyers Communiction Group) •Facilitative Leadership (Interaction Associates) •various presenter workshops, briefings, trainings References Inside my profile on LinkedIn: Skill set FPGA, ASIC, XILINX, VHDL, Verilog, Pascal, Modula2, Ada, C, SUN, Solaris, Apple, Windows NT, sys- tem administration, PCB layout, signal integrity, Microsoft, TCP/IP, framer, system design, verification, syn- by thesis, simulation, RTL, Synopsys, Cadence, Mentor, Aldec, ModelSim, Synplicity, Exemplar, Active-HDL, keywords CAD, EDA, FlexLM, licensing, SunOS, ULTRIX, Linux, VMS, CMOS, standard cells, gate arrays, Silvar- Lisco, XACT, PDF, Acrobat, Adobe, FrameMaker, Protel, ORCAD, HTML, PHP, csh, cshell, bourneshell, kornshell, SOC, digital design, LAN, WAN, gateway, switch, router, engineer, VoIP, packet processing, DDR, SRAM interface, DDR RAM interface, Transputer, INMOS, Viewlogic, WorkView, Dash FutureNet, Super- conductor, german, mentoring, patent, consulting, Dipl.-Ing., MSEE, system administration, network admin- istrator, wirespeed, project management, Blue Iguana, HDMI, SerDes, teaching, international, presentations, tradeshow representations, adaptive computing, DSP, digital filter, multi-lingual, ATM, SONET, SDH, DLL, clock recovery, logic design, ASIC design, heterogeneous networks, gate level, circuit design, Hell, Linotype, Heidelberg, repro graphic, scanner, recorder, graphic processing, picture processing, medical technology, optical network, Globetrotter, video processing, speech processing, sound processing, VLSI, HDL, Vera, tim- ing analysis, design flow, tool configuration, design flow administration, testbenches, TCL/TK, object-ori- ented design, OOHD, multi-million gates, PLL, CDR, transceiver, double data rate, chipscope, methodology, hierarchical, modular, symmetrical, locality, power management, place, route, P&R, physical layout, floor planning, memory compiler, timing-driven, logic-synthesis, physical verification, DRC, LVS, schematic, logic simulation, EDIF, SDF, SMES, ATMEL, prototype, DFT, BIST, BILBO, LFSR, scan path, dual citizen- ship, signature analysis, synchronous design, scripting, scripts, shell scripts, MAC, OSI model, IEEE, audio, VAR, behavioral, model, emulation, MMI, Mietec, GIBSON, GUITAR, MaGIC, mixed signal, mixed-signal, codec, real-time audio Dual US: United States citizen EU: German citizen (working permit for the whole European Union) citizenship Version 2011. (the latest version of this resume can always be found at: http://www.asic.ccVersion: 2011. Copyright 1999-2011 for structure, layout, and content by Andreas Schmidt (ASIC.CC) Page 4 of 4