Hard IP Core design | Convolution Encoder
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Hard IP Core design | Convolution Encoder

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Presentation of our major project during b.tech. Staring from requirements, we had developed soft ip and then hard ip for convolution encoder.

Presentation of our major project during b.tech. Staring from requirements, we had developed soft ip and then hard ip for convolution encoder.

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Hard IP Core design | Convolution Encoder Hard IP Core design | Convolution Encoder Presentation Transcript

  • Development of Hard Intellectual Property core for Convolution Encoder Guide: Prof. Usha Mehta Prepared By:- Archit (09bec101) Aalay (09bec025)
  • Steps Selection of IP-Core and its theory and study of IP-core VHDL and Verilog coding Implementing code on FPGA kit Layout MICROWIND software tool Comparison and readings
  • Review 1 Selection of IP-Core and its theory and study of IP-core VHDL and verilog code for state machine apprach
  • About convolution codes Error Correcting Code Sequential Codes Constraint length (k) (trade-off) Rate of Coder (r) (trade-off) Why so named ? Applications (wireless communication) Popular Codes (k=7; r=1/2)
  • Applications Wireless Standards : W-LAN, Wi-Max etc. Satellite communication Cellular Standards : GSM, CDMA, 3G etc.
  • Standard Polynomials
  • Example
  • Block Diagram View
  • State Machine View
  • Constraint length 7
  • Constraint length 7
  • Review 2 Both VHDL and Verilog codes are ready with block diagram approach Constraint Length 7; Rate ½ Results showing comparison with Coregen(Core Generation) Each component is made in microwind Dimension of Each Component made Also a C code for convolution coder is made to easy testing
  • Proposed Code VHDL Verilog RTL view
  • Proposed code
  • Proposed Code
  • Proposed Code
  • Coregen
  • Coregen
  • Comparison with Coregen
  • Components required No of components No of Transistors DFF 6 16 XOR2 4 4 XOR_regular 1 6
  • Layouts of each component
  • Layouts of DFF
  • Layouts of 2 input Xor XOR_2 Complements Available
  • Layouts of 2 input Xor XOR Regular Complements Not Available
  • Design schematic
  • Comparison with Verilog Compilation Using Verilog coding  63 NMOS  51 PMOS  114 Total  Buffers not provided  Metalization 3 levels  Area = 575.28 µm  Highly rectangular Proposed Hard IP  60 NMOS  60 PMOS  120 total  Bufferes provided  Metalization 2 layers  Area 186.3 square µm  Almost square
  • Review 3 Floor Planning Complete Layout SPICE simulation
  • Floor Planning
  • Floor Planning
  • Floor Planning
  • Pinout
  • Final Layout
  • Simulation
  • Spice Netlist Exported from Microwind Got introduced to Tanner, Mentor Graphics and SPICE syntax Readings are taken from Mentor Graphics
  • Readings Maximum Average Power dissipation 0.622 mW 0.130 mW Idd 0.519 mA 0.109 mA X to Z1 48.706 ps 38.347 ps X to Z2 66.721 ps 40.2042 ps Clk to Z1 49.974 ps 36.343 ps Clk to Z2 57.999 ps 38.493 ps Core Size : 186.3 sq. um Supply : 1.2 V
  • Summary Xilinx ISE: – Verilog, RTL, Spartan 3 kit DSCH: – Gate level, Transistor level Microwind: – Floor planning, Layout Mentor Graphics: – SPICE Simulation
  • Conclusion Great learnings – VLSI Industry – Coregen Implementation – Verilog Coding Better than Xilinx Coregen Better than direct Verilog Implementation
  • References Basics Of CMOS Cell Design – Etienne Sicard, Sonia Delmas Bendhia CMOS VLSI DESIGN : A Circuit and System Perspective – Neil H. E. Weste, David Harris, Ayan Banerjee CMOS Digital Integrated Circuit,3/E – Sung-Mo-Kang, Yusuf Leblebici
  • References Spice User Manual Draft 10 T-Spice 12 user guide – Tanner EDA tools Open Source Semiconductor Core Licesing – Harvard Journal of Law and Technology Digital Design 4th Edition – Morris Mano
  • Questions ??
  • Thank you ! Prof. Usha Mehta Mr. Dharmesh Patel Mr. Prasann Shukla Nirma University and All Professors – 4 years of great learning