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Apple A5 Processor
 

Apple A5 Processor

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A presentation describing the features of Apple A5 processor.

A presentation describing the features of Apple A5 processor.

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  • SMID-Single Instruction Multiple Data

Apple A5 Processor Apple A5 Processor Presentation Transcript

  • What is A5 processor? 0 Systems-on-a-chip (SoCs) 0 Designed by Apple Inc. 0 Fabricated by Samsung to replace the Apple A4. 0 Commercially debuted with the release of Apple's iPad 2 tablet. 0 Also powers the iPhone 4S, and iPad (3rd generation).
  • Details of A5 0 Chip based upon the dual- core ARM Cortex-A9 Core CPU. 0 CPU - twice as powerful as the original iPad. 0 NEON SIMD accelerator and a dual core PowerVR SGX543MP2 GPU 0 Contains 512 MiB of lowpower DDR2 RAM clocked at 533 MHz
  • GPU 0 Graphical Processing Unit (GPU): 0 Circuit 0 Buffers images in a frame and sets it into motion 0 So the video or images can be viewed in the home screen or display 0 GPU up to seven times as powerful as, the Apple A4. 0 Capacity to move 1 billion pixels per second 0 Image Signal Processor unit (ISP) 0 Advanced image post-processing 0 Face detection, white balance and automatic image stabilization
  • Processor view from back of chip
  • Apple A5 (S5L8940) 0 1st version A5 chip-iPhone 4S and iPad 2. 0 Manufacturing process: 45 nm having 122.2 mm2 of die area 0 Package on package (PoP) together with RAM. 0 IC packaging technique 0 Combines discrete logic and memory ball grid array packages 0 Packages arranged one above the other 0 Standard interface for routing the signals in between 0 Main benefit - Motherboard space savings
  • Apple A5 (S5L8942) 0 2nd version of A5 chip - Apple TV (3rd generation),& iPad 2(2nd generation) 0 Manufacturing process: 32 nm fabrication 0 Measures nearly 41% smaller than 1st generation A5, at 69.6 mm² die area. 0 Package on package (PoP) together with RAM.
  • Apple A5X (S5L8945) 0 A5X chip-iPad (3rd generation) 0 Dual-core CPU at 1 GHz 0 Quad-core PowerVR GPU 0 Not packaged together with the RAM. 0 Lithography: 45 nm to 32 nm. 0 L1 cache =32KiB instruction+32KiB data 0 L2 cache =1MiB 0 Silicon die size: 165 mm2 0 210% larger than 53.3 mm2 die area of the original A4.