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tHIS IS TO STUDY THE ADDERS

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2. 2. Acknowledgement <ul><li>Slides taken from http:// bwrc.eecs.berkeley.edu/IcBook/index.htm </li></ul><ul><li>which is the web-site of “Digital Integrated Circuit – A Design Perspective” by Rabaey, Chandrakasan, Nicolic </li></ul>
3. 3. Outline <ul><li>Background / Basics of Adders </li></ul><ul><li>Ripple Carry Adder </li></ul>
4. 4. A Generic Digital Processor
5. 5. Building Blocks for Digital Architectures Arithmetic unit - Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus
6. 6. Bit-Sliced Design
7. 7. Bit-Sliced Datapath
8. 8. Itanium Integer Datapath Fetzer, Orton, ISSCC’02
11. 11. Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A  B Delete = A B Can also derive expressions for S and C o based on D and P Propagate (P) = A  B Note that we will be sometimes using an alternate definition for
12. 12. The Ripple-Carry Adder Worst case delay linear with the number of bits Goal: Make the fastest possible carry path circuit t d = O( N ) t adder = ( N-1 ) t carry + t sum
13. 13. Complimentary Static CMOS Full Adder 28 Transistors
14. 14. Inversion Property
15. 15. Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property
16. 16. A Better Structure: The Mirror Adder
17. 17. Mirror Adder Stick Diagram
18. 18. The Mirror Adder <ul><ul><ul><li>The NMOS and PMOS chains are completely symmetrical . A maximum of two series transistors can be observed in the carry-generation circuitry. </li></ul></ul></ul><ul><ul><ul><li>When laying out the cell, the most critical issue is the minimization of the capacitance at node C o . The reduction of the diffusion capacitances is particularly important. </li></ul></ul></ul><ul><ul><ul><li>The capacitance at node C o is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . </li></ul></ul></ul><ul><ul><ul><li>The transistors connected to C i are placed closest to the output. </li></ul></ul></ul><ul><ul><ul><li>Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size. </li></ul></ul></ul>
19. 19. Transmission Gate Full Adder
20. 20. Manchester Carry Chain
21. 21. Manchester Carry Chain
22. 22. Manchester Carry Chain Stick Diagram
23. 23. Carry-Bypass Adder Also called Carry-Skip
24. 24. Carry-Bypass Adder (cont.) t adder = t setup + Mt carry + ( N/M -1) t bypass + ( M -1) t carry + t sum
25. 25. Carry Ripple versus Carry Bypass
27. 27. Carry Select Adder: Critical Path
28. 28. Linear Carry Select
29. 29. Square Root Carry Select
30. 30. Adder Delays - Comparison
31. 31. LookAhead - Basic Idea