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System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
System On Chip
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System On Chip

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  • 1. Core Based SOC Design Prof. Anish Goel
  • 2. SoC : System on Chip System  A collection of all kinds of components and/or subsystems that are appropriately interconnected to performance the specified functions for end users  A SoC design is a “product creation process” Which  Starts at identifying the end-user needs  Ends at delivering a product with enough functional satisfaction to overcome the payment from the end-user 2 SOC Design Prof. Anish Goel
  • 3. IP-Based Design3 SOC Design Prof. Anish Goel
  • 4. SOC Also named System-on-a Chip. System LSI, System-on- Silicon, System-on-… It used to be System-on-aboard, or System-in-a cabinet, or System-in-package (SIP) System Hardware Analog : ADC/DAC, PLL, TxRx, RF Digital : Processor, Interface, Accelerator Storage : SRAM, DRAM, FLASH, ROM Software : RTOS, IP Device Driver, Application 4 SOC Design Prof. Anish Goel
  • 5. What is an SoC?  An SoC must contain:  Portable / reusable IP  Embedded CPU  Embedded Memory  Real World Interfaces  (USB, PCI, Ethernet)  Software (both on- chip and off)  An SoC may contain:  Programmable HW  (FPGAs, Flash)  Mixed-signal Blocks  Sensors  Not just an ASIC !5 SOC Design Prof. Anish Goel
  • 6. Benefits of Using SoC Reduce overall system cost Increase performance Lower power consumption Reduce size 6 SOC Design Prof. Anish Goel
  • 7. Evolution of Semiconductor DeviceTechnology7 SOC Design Prof. Anish Goel
  • 8. Evolution of Silicon Design8 SOC Design Prof. Anish Goel
  • 9. Challenges in SoC Era Time-to-market  Process roadmap acceleration  Consumerization of electronic devices Complex systems  µCs, DSPs, HW/SW, SW protocol stacks, RTOS’s, digital/analog IPs, On-chips buses Deep submicron effects  Crosstalk electron migration, wire delays, mask costs 9 SOC Design Prof. Anish Goel
  • 10. Heterogeneous SoC Technology10 SOC Design Prof. Anish Goel
  • 11. SOC Design Requirement System Support & Portability Open Industry Standard Testability Process Dependency Design Methodology Price/Performance/Power 11 SOC Design Prof. Anish Goel
  • 12. How to Conquer the Complexity Use a known real entity  A pre-designed component (IP reuse)  A Platform (architecture reuse) Partition  Based on functionality  Hardware and software Modeling  At different Level  Consistent and accurate 12 SOC Design Prof. Anish Goel
  • 13. SOC Current Challenge IP Availability  Good and qualified IP from qualified vendors  One stop IP search engine & service System Complexity  Analog IP process dependency  Advanced process maturity  System software development - IP coverage Verification & Failure Analysis  Lack of system simulation models  IP testability - built-in self testing  Testing equipment limitation 13 SOC Design Prof. Anish Goel
  • 14. A Representative 2G/2.5G Cell Phone14 SOC Design Prof. Anish Goel
  • 15. Example of Complex System-on-Chip15 SOC Design Prof. Anish Goel
  • 16. SoC Architecture16 SOC Design Prof. Anish Goel
  • 17. SoC Applications Communication  Digital cellular phone  Networking Computer  PC/Workstation  Chipsets Consumer  Set top box  Game box  Digital camera 17 SOC Design Prof. Anish Goel
  • 18. Internet Age - Very DemandingApplications18 SOC Design Prof. Anish Goel
  • 19. Innovations that Enable SOC Integration19 SOC Design Prof. Anish Goel
  • 20. Traditional waterfall ASIC design flow20 SOC Design Prof. Anish Goel
  • 21. Differences in Design Between IC and IP Limitation of IC design  Number of I/O pin  Design and Implement all the functionality in the silicon Soft IP  No limitation on number of I/O pin  Parameterized IP Design : design all the functionality in HDL code but implement desired parts in the silicon  IP compiler/Generator : select what you want !!  More high level auxiliary tools to verify design  More difficult in chip-level verification Hard IP  No limitation on number of I/O pin  Provide multiple level abstract model  Design and Implement all the functionality in the layout 21 SOC Design Prof. Anish Goel
  • 22. SoC Design Flow22 SOC Design Prof. Anish Goel
  • 23. Summary SoC technology and IP design have become a dominant focus in todays global ICs industry. SoC integration has potential to continue IC cost reduction and to perpetuate growth of personal internet products Complex SOC or IP Core designs has created new challenges IP- based or Platform-Based Design Methodology will be studied 23 SOC Design Prof. Anish Goel

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