Switching Tech And Data Link

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Switching Tech And Data Link

  1. 1. Switching Technologies & Data Link Layer<br />Prof. Anish Goel<br />
  2. 2. Network: Links & switches<br />Circuit consists of dedicated resources in sequence of links & switches across network<br />Circuit switch connects input links to output links<br />2<br /> Switching Technologies and DLL Anish Goel<br />
  3. 3. Circuit Switch Types<br /> Space-Division switches<br />Provide separate physical connection between inputs and outputs<br />Crossbar switches<br />Multistage switches<br /> Time-Division switches<br />Time-slot interchange technique<br />Time-space-time switches<br /> Hybrids combine Time & Space switching<br />3<br /> Switching Technologies and DLL Anish Goel<br />
  4. 4. Crossbar Space Switch<br />N x N array of crosspoints<br /> Connect an input to an output by closing a crosspoint<br />Nonblocking: Any input can connect to idle output (definition of nonblocking)<br /> Complexity: N² crosspoints<br />4<br /> Switching Technologies and DLL Anish Goel<br />
  5. 5. Multistage Space Switch<br /> Large switch built from multiple stages of small switches<br /> The n inputs to a first-stage switch share k paths through intermediate crossbar switches <br />Larger k (more intermediate switches) means more paths to output<br /> In 1950s, Clos asked, “How many intermediate switches required to make switch nonblocking?”<br />5<br /> Switching Technologies and DLL Anish Goel<br />
  6. 6. Clos Non-Blocking Condition: k=2n-1<br /> Request connection from last input to input switch j to last output in output switch m<br /> Worst Case: All other inputs have seized top n-1 middle switches AND all other outputs have seized next n-1 middle switches<br /> If k=2n-1, there is another path left to connect desired input to desired output<br />6<br /> Switching Technologies and DLL Anish Goel<br />
  7. 7. Minimum Complexity Clos Switch<br />7<br /> Switching Technologies and DLL Anish Goel<br />
  8. 8. Time-Slot Interchange (TSI) Switching<br /> Write bytes from arriving TDM stream into memory<br /> Read bytes in permuted order into outgoing TDM stream<br /> Max # slots = 125 msec / (2 x memory cycle time), where memory cycle time is the time required for reading or writing a frame per slot.<br />8<br /> Switching Technologies and DLL Anish Goel<br />
  9. 9. Time-Space-Time Hybrid Switch<br /> Use TSI in first & third stage; Use crossbar in middle<br /> Replace n input x k output space switch by TSI switch that takes n slot input frame and switches it to k-slot output frame<br />9<br /> Switching Technologies and DLL Anish Goel<br />
  10. 10. Flow of time slots between switches<br /> The first slot corresponds to the first output line out of each of the first stage switch.<br /> Only one space switch active in each time slot<br />10<br /> Switching Technologies and DLL Anish Goel<br />
  11. 11. Time-Share the Crossbar Switch<br /> Interconnection pattern of space switch is reconfigured every time slot<br /> Very compact design: fewer lines because of TDM & less space because of time-shared crossbar<br />11<br /> Switching Technologies and DLL Anish Goel<br />
  12. 12. Example: A->2, B->4, C->1, D->3<br />12<br /> Switching Technologies and DLL Anish Goel<br />
  13. 13. Example: T-S-T Switch Design<br />For N = 960<br /> Single stage space switch ~ 1 million crosspoints<br /> T-S-T<br /> Let n = 120 N/n = 8 TSIs<br />k = 2n – 1 = 239 for non-blocking<br /> Pick k = 240 time slots<br /> Need 8x8 time-multiplexed space switch<br />For N = 96,000<br /> T-S-T<br /> Let n = 120 k = 239<br />N / n = 800<br /> Need 800x800 space switch<br />13<br /> Switching Technologies and DLL Anish Goel<br />
  14. 14. Data Link Protocols<br />14<br /> Switching Technologies and DLL Anish Goel<br />
  15. 15. DLL Framing<br />15<br /> Switching Technologies and DLL Anish Goel<br />
  16. 16. Character-based Framing Synchronization<br /> Used when frames consist of integer number of bytes<br /> Asynchronous transmission systems using ASCII to transmit printable characters<br /> Octets with HEX value &lt;20 are nonprintable<br /> Special 8-bit patterns used as control characters<br /> STX (start of text) = 0x02; ETX (end of text) = 0x03;<br /> Byte used to carry non-printable characters in frame<br /> DLE (data link escape) = 0x10<br /> DLE STX (DLE ETX) used to indicate beginning (end) of frame<br /> Insert extra DLE in front of occurrence of DLE STX (DLE ETX) in frame<br /> All DLEs occur in pairs except at frame boundaries<br />16<br /> Switching Technologies and DLL Anish Goel<br />
  17. 17. Framing & Bit Stuffing<br /> Frame delineated by flag (01111110) character<br /> HDLC uses bit stuffing to prevent occurrence of flag 01111110 inside the frame<br /> Transmitter inserts extra 0 after each consecutive five 1s inside the frame<br /> Receiver checks for five consecutive 1s<br />17<br /> Switching Technologies and DLL Anish Goel<br />
  18. 18. Example: Bit stuffing & de-stuffing<br />18<br /> Switching Technologies and DLL Anish Goel<br />
  19. 19. Frame & Byte Stuffing<br /> PPP uses similar frame structure as HDLC, except<br /> Protocol type field<br /> Payload contains an integer number of bytes<br /> PPP uses the same flag, but uses byte stuffing<br /> Problems with PPP byte stuffing<br /> Size of frame varies unpredictably due to byte insertion<br /> Malicious users can inflate bandwidth by inserting 7D & 7E<br />19<br /> Switching Technologies and DLL Anish Goel<br />
  20. 20. Byte-Stuffing in PPP<br />PPP is character-oriented version of HDLC<br /> Flag is 0x7E (01111110)<br /> Control escape 0x7D (01111101)<br /> Any occurrence of flag or control escape inside of frame is replaced with 0x7D followed by<br />original octet exclusive-ORed with 0x20 (00100000)<br /> At the receiver, remove 7D and XOR the next character with 0x20<br />20<br /> Switching Technologies and DLL Anish Goel<br />
  21. 21. Generic Framing Procedure<br /> GFP combines frame length indication with CRC<br /> PLI indicated length of frame (the size of GFP payload area), then simply count characters<br />cHEC (includes CRC-16) protects against errors in count field (single-bit error correction + multiple bits error detection)<br /> GFP designed to operate over octet-synchronous physical layers (e.g. SONET)<br /> Frame-mapped mode for variable-length payloads: Ethernet<br /> Transparent mode carries fixed-length payload: storage devices<br />21<br /> Switching Technologies and DLL Anish Goel<br />
  22. 22. GFP Synchronization & Scrambling<br /> Synchronization in three-states<br />Hunt state: examine 4-bytes to see if CRC ok<br /> If no, move forward by one-byte (assuming octet synchronous transmission is given at the physical layer).<br /> If yes, move to pre-sync state<br />Pre-sync state: tentative PLI indicates next frame<br /> If N successful frame detections, move to sync state<br /> If no match, go to hunt state<br />Sync state: normal state<br /> Validate PLI/cHEC, extract payload, go to next frame<br /> Use single-error correction<br /> Go to hunt state if non-correctable error<br /> Scrambling<br /> Payload is scrambled to prevent malicious users from inserting long strings of 0s which cause SONET equipment to lose bit clock synchronization (as discussed in line code section)<br />22<br /> Switching Technologies and DLL Anish Goel<br />

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