PLD’s and Introduction to the       Altera Cyclone II FPGA                  Prof. Anish Goel
Programmable Logic Device Black Box2                PLDs and Altera Cyclone FPGA   Prof. Anish Goel
General PLA Structure3              PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Gate Level PLA Structure4               PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Customary Schematic of a PLA5              PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Typical PLA Output Circuitry6               PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Structure of a CPLD7              PLDs and Altera Cyclone FPGA   Prof. Anish Goel
A Section of a CPLD8               PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Structure of an FPGA9              PLDs and Altera Cyclone FPGA   Prof. Anish Goel
A Two-Input Lookup Table10             PLDs and Altera Cyclone FPGA   Prof. Anish Goel
A Three-Input Lookup Table11             PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Inclusion of a flip-flop With an LUT12                PLDs and Altera Cyclone FPGA   Prof. Anish Goel
A Section of a Programmed FPGA13             PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Pass transistor Switches in an FPGA14               PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Cyclone II General Features    Contain a two-dimensional row- and column-based     architecture to implement custom logic...
Cyclone II General Features (continued)    Cyclone II devices provide a global clock network and up     to four phase-loc...
Cyclone II General Features (continued)    M4K memory blocks are true dual-port memory blocks with     4K bits of memory ...
Altera Cyclone II Programmable Device18                PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Cyclone II EP2C20 Device Block Diagram19                PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Cyclone II Logic Element (LE)    A four-input look-up table (LUT), which is a function generator     that can implement a...
Cyclone II Logic Element (LE)21              PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Cyclone II LAB Structure22              PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Embedded Memory (M4K Block)    4,608 RAM bits    Memory Configuration     True dual-port memory     Simple dual-port mem...
M4K RAM Block LAB Row Interface24              PLDs and Altera Cyclone FPGA   Prof. Anish Goel
Cyclone II IOE Structure25             PLDs and Altera Cyclone FPGA   Prof. Anish Goel
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Ip core example

  1. 1. PLD’s and Introduction to the Altera Cyclone II FPGA Prof. Anish Goel
  2. 2. Programmable Logic Device Black Box2 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  3. 3. General PLA Structure3 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  4. 4. Gate Level PLA Structure4 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  5. 5. Customary Schematic of a PLA5 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  6. 6. Typical PLA Output Circuitry6 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  7. 7. Structure of a CPLD7 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  8. 8. A Section of a CPLD8 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  9. 9. Structure of an FPGA9 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  10. 10. A Two-Input Lookup Table10 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  11. 11. A Three-Input Lookup Table11 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  12. 12. Inclusion of a flip-flop With an LUT12 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  13. 13. A Section of a Programmed FPGA13 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  14. 14. Pass transistor Switches in an FPGA14 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  15. 15. Cyclone II General Features Contain a two-dimensional row- and column-based architecture to implement custom logic Column and row interconnects of varying speeds provide signal interconnects between logic array blocks (LABs), embedded memory blocks, and embedded multipliers The logic array consists of LABs, with 16 logic elements (LEs) in each LAB An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device 15 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  16. 16. Cyclone II General Features (continued) Cyclone II devices provide a global clock network and up to four phase-locked loops (PLLs)  Consists of up to 16 global clock lines that drive throughout the entire device  Can provide clocks for all resources within the device, such as input/output elements (IOEs), LEs, embedded multipliers, and embedded memory blocks  Global clock lines can also be used for other high fan-out signals Cyclone II PLLs provide general-purpose clocking with clock synthesis and phase shifting as well as external outputs 16 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  17. 17. Cyclone II General Features (continued) M4K memory blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits)  Provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide  Arranged in columns across the device in between certain LABs Each embedded multiplier block  Can implement up to either two 9 × 9-bit multipliers, or one 18 × 18- bit multiplier  Embedded multipliers are arranged in columns across the device Each Cyclone II device I/O pin is fed by an IOE located at the ends of LAB rows and columns around the periphery of the device  Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals 17 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  18. 18. Altera Cyclone II Programmable Device18 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  19. 19. Cyclone II EP2C20 Device Block Diagram19 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  20. 20. Cyclone II Logic Element (LE) A four-input look-up table (LUT), which is a function generator that can implement any function of four variables A programmable register A carry chain connection  A fast interconnect between adjacent LABs A register chain connection  A fast, registered, connection between adjacent LEs The ability to drive all types of interconnects:  Local, row, column, register chain, and direct link interconnects Support for register packing  Combining a register with combinational logic in a design Support for register feedback  Feedback from flip-flop output back into the LUT 20 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  21. 21. Cyclone II Logic Element (LE)21 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  22. 22. Cyclone II LAB Structure22 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  23. 23. Embedded Memory (M4K Block) 4,608 RAM bits Memory Configuration True dual-port memory Simple dual-port memory Single-port memory Byte enable Parity bits Common Functions Dual Port Memory Configuration 23 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  24. 24. M4K RAM Block LAB Row Interface24 PLDs and Altera Cyclone FPGA Prof. Anish Goel
  25. 25. Cyclone II IOE Structure25 PLDs and Altera Cyclone FPGA Prof. Anish Goel

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