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3 hour tutorial on phase locked loop.

3 hour tutorial on phase locked loop.

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Phase locked loop Phase locked loop Presentation Transcript

  • Phase Locked Loop (PLL) Aniruddha Chandra ECE Department, NIT Durgapur, WB, India. <aniruddha.chandra@ieee.org> Jan 24, 2009ECE Department, Winter School on NIT Durgapur VLSI Systems Design
  • VLSI Outline Systems Design 24/01/09  Synchronization  PLL Basics  Analog PLL  Digital PLL  TDTL FPGA ImplementationA. Chandra, NIT DGP – PLL 2/50
  • VLSI Synchronization ??? Systems Design 24/01/09 Concept Attribute Synchronization Frequency/ phase Urban traffic Vehicle speed  In heavy traffic we are forced to match our speed to that of the car in front of us and should also try to avoid sudden braking so as not to frighten the driver behind us.A. Chandra, NIT DGP – PLL 3/50
  • VLSI Synchronization ??? Systems Design 24/01/09 Concept Attribute Synchronization Frequency/ phase Orchestra Scale of note  In a symphony orchestra, the reference is the conductor, and all musicians attempt to reproduce the beat as set by the conductor’s baton.A. Chandra, NIT DGP – PLL 4/50
  • VLSI Systems Design 24/01/09 Synchronization We take it for grantedA. Chandra, NIT DGP – PLL 5/50
  • VLSI Synchronization Systems Design 24/01/09 What happens without it? ExchangeA. Chandra, NIT DGP – PLL 6/50
  • VLSI Synchronization Systems Design 24/01/09 What happens without it? ExchangeA. Chandra, NIT DGP – PLL 7/50
  • VLSI Synchronization Systems Design 24/01/09 What happens without it?A. Chandra, NIT DGP – PLL 8/50
  • VLSI Synchronization Hierarchy Systems Design 24/01/09 Carrier Synchronization Coherent demodulation – phase/ frequency Non-coherent demodulation – frequency Multi Carrier systems – sub-carrier Symbol Synchronization Integrator, Decision device Frame Synchronization Multiple access (TDMA), FEC (Block coding) Network Synchronization Transmitter synchronization – Satellite, GPS, CDMAA. Chandra, NIT DGP – PLL 9/50
  • VLSI Systems Design 24/01/09 Phase Locked Loop (PLL) Building block for all synchronization systemA. Chandra, NIT DGP – PLL 10/50
  • VLSI PLL - Basics Systems Design 24/01/09 What is PLL? PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in the frequency as well as in phase. This is the action of a PLL Oscillator output Reference input These look like pointless operations!  Track average phase (& frequency)/ period inputA. Chandra, NIT DGP – PLL 11/50
  • VLSI PLL - Basics Systems Design 24/01/09 PLL types Phase and Frequency locked  coherent demodulation Oscillator output Reference input Frequency locked, constant Phase difference  non-coherent demodulation Oscillator output Reference inputA. Chandra, NIT DGP – PLL 12/50
  • VLSI PLL - Applications Systems Design 24/01/09 Clock phase adjustment in μP Time-to-Digital converters (TDC) Frequency synthesis Motor speed control Frequency modulation/ demodulation Jitter reduction, Skew suppression, Clock recoveryA. Chandra, NIT DGP – PLL 13/50
  • VLSI Turning the pages of History Systems Design 24/01/09 1922-27: Oscillator synchronization - Appleton, VanderPol 1932: Publication on the PLL concept - H. de Bellescise 1932: British scientists develop the homodyne/ synchrodyne detection (AFC) 1943: PLL applied in TV - vertical and horizontal scan 1965: Analog PLL devices appeared 1970: Digital PLL introduced - IC 565, CD 4046 1980-90: All-digital PLL (ADPLL) was invented. Software controlled PLL (SPLL) became relity.A. Chandra, NIT DGP – PLL 14/50
  • VLSI Systems Design 24/01/09 Analog Phase Locked Loop (APLL)A. Chandra, NIT DGP – PLL 15/50
  • VLSI Analog PLL (APLL) Systems Design 24/01/09  In synchronized or locked state, the phase error between the oscillator’s output and the reference signal is either zero or an arbitrary constant. When phase error builds up, the oscillator is tuned by a control mechanism to reduce the phase error. The components of a PLL: VCO, PD, and LF.A. Chandra, NIT DGP – PLL 16/50
  • VLSI APLL - Analysis Systems Design 24/01/09 The reference (or input signal) v1 ( t ) = V1 cos( ω1t ) The output signal of the VCO v2 ( t ) = V2 cos( ω 2 t ) with ω2 ( t ) = ω0 + K 0 v f ( t ) , where ωo is the centre frequency of the VCO, Ko is the VCO gain, and vf (t) is the output signal of loop filterA. Chandra, NIT DGP – PLL 17/50
  • VLSI APLL - Analysis Systems Design 24/01/09 The phase error at PD θ e ( t ) = ( ω1 − ω 2 ) t PD output signal vd ( t ) = K d θ e ( t ), where Kd is the PD gain vd (t) consists of a dc component and a superimposed ac component vf (t) is delayed version of vd (t) with ac removedA. Chandra, NIT DGP – PLL 18/50
  • VLSI APLL – Components Systems Design 24/01/09 Phase Detector (PD) PD compares the phases of the input and output signals and generate an error signal proportional to the phase deviation. A mixer (analog multiplier/ balanced modulator) generates the sums and differences of the frequencies at its input terminals.A. Chandra, NIT DGP – PLL 19/50
  • VLSI APLL – Components Systems Design 24/01/09 Phase Detector (PD)  Superior noise performance  Operates on the entire amplitude of the input and VCO signals rather than quantizing them to 1 bit  Best suited for PLL applications in the microwave frequency range as well as in low noise frequency synthesizers  Loop gain depends on signal amplitude  Non-linear response due to non-idealities in the circuitA. Chandra, NIT DGP – PLL 20/50
  • VLSI APLL – Components Systems Design 24/01/09 Voltage Controlled Oscillator (VCO) VCO produces an oscillation whose frequency can be controlled through some external voltage. VCO types Ring oscillator - Odd number of inverters connected in a feedback loop. Relaxation oscillator - Generates square wave using Schmitt trigger.A. Chandra, NIT DGP – PLL 21/50
  • VLSI APLL – Components Systems Design 24/01/09 VCO types (Contd.) Resonant oscillator - Resonant circuit in the positive feedback path of a voltage to current amplifier. Crystal Oscillator YIG Oscillator - YIG (Yttrium, Iron and Garnet) spheres, due to the ferrite properties, resonate at μ- wave frequencies when A simple resonant circuit VCO, where immersed in a magnetic the frequency is controlled by adjusting the reverse bias of the varactor diode C1 field.A. Chandra, NIT DGP – PLL 22/50
  • VLSI APLL – Components Systems Design 24/01/09 Loop Filter PLLs are mostly second order and as the VCO is modeled as an integrator, loop filters are of the lead-lag type. More specifically, the loop filter contains an integrator which is able to track a phase ramp, and this corresponds to tracking a step in frequency. Passive lead-lag filter Active lead-lag filterA. Chandra, NIT DGP – PLL 23/50
  • VLSI APLL – Performance Metrics Systems Design 24/01/09 Hold Range  The hold range, is defined as the frequency range over which the PLL is able to statically maintain phase tracking Lock Range  The lock range, is defined as the frequency range within which the PLL locks within one single-beat note between the reference frequency and output frequency.A. Chandra, NIT DGP – PLL 24/50
  • VLSI Systems Design 24/01/09 Digital Phase Locked Loop (DPLL)A. Chandra, NIT DGP – PLL 25/50
  • VLSI Why DPLL? Systems Design 24/01/09 Superiority in performance APLLs can’t operate at very low frequencies. The analog LPF struggles while extracting the lower frequency component, as it needs larger time for better frequency resolution. Speed Self-acquisition of APLLs is often slow, while DPLLs can achieve locking within few cycles. Reliability VCO is sensitive to temperature and power supply variations. Analog multipliers are sensitive to DC drifts. Reduction in size and costA. Chandra, NIT DGP – PLL 26/50
  • VLSI DPLL Development Systems Design 24/01/09  Sinusoidal Digital PLL (1970)  Digital tan-lock loop (1982)  Time-delay digital tan-lock loopA. Chandra, NIT DGP – PLL 27/50
  • VLSI DPLL Schematic Systems Design 24/01/09 Digital PDA. Chandra, NIT DGP – PLL 28/50
  • VLSI DPLL – Components Systems Design 24/01/09 Phase Error Detector (PED) Classification based on PED type • Flip-flop DPLL 2. The Nyquist-rate DPLL 3. The lead-lag DPLL or, binary-quantized DPLL 4. Exclusive-OR DPLL 5. Zero-crossing DPLLA. Chandra, NIT DGP – PLL 29/50
  • VLSI Flip-flop DPLL Systems Design 24/01/09  Comparator - convert sinusoidal input into a square wave  Q output - duration when Q = 1 is proportional to phase error Phase detector  Counter clock - frequency 2M × fo fo = DCO center frequency 2M = number of quantization levels of the phase error over period of 2πA. Chandra, NIT DGP – PLL 30/50
  • VLSI Flip-flop DPLL Systems Design 24/01/09  Counter - starts counting on the positive-going edge of the flip-flop waveform.  The content of the counter, N , which is proportional to the o phase error, is applied to digital filter. Phase detector  The output of the digital filter K controls the period of the DCO  DCO - programmable divide- by-K counterA. Chandra, NIT DGP – PLL 31/50
  • VLSI DPLL – Components Systems Design 24/01/09 Digital Controlled Oscillator (DCO)A. Chandra, NIT DGP – PLL 32/50
  • VLSI Digital Controlled Oscillator (DCO) Systems Design 24/01/09 DCO Components Binary Subtrator  Programmable counter  Binary subtractor  Zero detector With each clock pulse counter decrements by one. When it reaches zero, the counter generates a pulse. This pulse is used to load the counter with M −K where K is input.A. Chandra, NIT DGP – PLL 33/50
  • VLSI Digital Controlled Oscillator (DCO) Systems Design 24/01/09 Binary Subtrator  DCO free-running frequency fo = fc /M where fc is the frequency of the counter clock.  The period between the (k−1) th and the kth pulse T(k) = (M − K) Tc where Tc = 1/ fcA. Chandra, NIT DGP – PLL 34/50
  • VLSI Systems Design 24/01/09 Sinusoidal DPLL Digital tan-lock loop (DTL) Time-delay digital tan-lock loop (TDTL)A. Chandra, NIT DGP – PLL 35/50
  • VLSI Digital tan-lock loop (DTL) Systems Design 24/01/09 Why DTL? Sinusoidal DPLL - sensitive to the variations in the input signal power and rather limited lock range Components 90o phase shifter, 2 samplers, PED, digital loop filter, DCOA. Chandra, NIT DGP – PLL 36/50
  • VLSI Digital tan-lock loop (DTL) Systems Design 24/01/09  Sampler I and II takes in-phase (I) and quadrature (Q) samples simultaneously.  Phase error at sampling instant is extracted by the tan −1 function. This phase error, modified by the digital filter, controls the period of DCO.A. Chandra, NIT DGP – PLL 37/50
  • VLSI Time-delay DTL (TDTL) Systems Design 24/01/09 Why TDTL? A digital Hilbert transformer introduces approximations and imposes limitations on the range of input frequencies, especially when implemented on a microprocessor. A constant time-delay may be used to produce a phase- shifted version of the incoming signal to reduce complexity.A. Chandra, NIT DGP – PLL 38/50
  • VLSI Improved TDTL - I Systems Design 24/01/09 Variable delay TDTL (VD-TDTL) The conflicting requirements of fast acquisition and wide locking range necessitate the inclusion of more than one time delay.A. Chandra, NIT DGP – PLL 39/50
  • VLSI Improved TDTL - II Systems Design 24/01/09 Adaptive gain TDTL (AG-TDTL) If a sudden change in input frequency drives the system to go outside the locking range, the system senses this error through the FSM and updates the gain of the digital filter to bring the operating point within the locking regionA. Chandra, NIT DGP – PLL 40/50
  • VLSI Improved TDTL - III Systems Design 24/01/09 Adaptive gain variable delay (AG-VD) TDTL Combining the best of two - faster acquisition, wider locking range and more resilience to frequency driftsA. Chandra, NIT DGP – PLL 41/50
  • VLSI Systems Design 24/01/09 TDTL FPGA ImplementationA. Chandra, NIT DGP – PLL 42/50
  • VLSI Platform Systems Design 24/01/09 Xtreme DSP development board  Virtex-II XC2V3000 chip with three million gates  Virtex-II XC2V80 for clocking and I/O management  Spartan-II interface FPGA for communicating with PC using the PCI bus/ USB. Xilinx System Generator serves as the software development platform. It consists of a Simulink library called the Xilinx Blockset, and software to Xtreme DSP Development translate a Simulink model into a Kit-II powered by a Virtex-II FPGA chip from Xilinx. hardware realization of the model.A. Chandra, NIT DGP – PLL 43/50
  • VLSI TDTL FPGA Implementation Systems Design 24/01/09A. Chandra, NIT DGP – PLL 44/50
  • VLSI CORDIC Arctangent Block Systems Design 24/01/09  The COordinate Rotational DIgital Computer (CORDIC) algorithm is an iterative method of calculating trigonometric and functions.  The CORDIC algorithm is used to implement the 4-quad tan−1(x / y) function of the phase detector, converging to angles between ± π within eleven system clock cycles.A. Chandra, NIT DGP – PLL 45/50
  • VLSI DCO Block Systems Design 24/01/09  The disadvantage of using divide-by-k counter is poor frequency resolution.  The DCO is implemented using a Direct Digital Synthesis (DDS) blockA. Chandra, NIT DGP – PLL 46/50
  • VLSI Systems Design 24/01/09 ReferencesA. Chandra, NIT DGP – PLL 47/50
  • VLSI Read more about this Systems Design 24/01/09  S. R. Al-Araji, Z. M. Hussain, and M. A. Al-Qutayri, Digital Phase Lock Loops: Architectures and Applications, Springer, Dordrecht, Netherlands, 2006.  W. F. Egan, Phase-Lock Basics, Wiley InterScience, John Wiley & Sons, New York, 1998.  R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications, McGraw-Hill, New York, 2003, 5th edition.A. Chandra, NIT DGP – PLL 48/50
  • VLSI Read even more about this Systems Design 24/01/09  M. Kihara, S. Ono, and P. Eskelinenesign, Digital Clocks for Synchronization and Communications, Artech House, Boston, London, 2003.  H. M. Berlin, Design of Phase-Locked Loop Circuits with Experiments, SAMS Publishers/ Longman Higher Education, 1978.  A. Blanchard, Phase-Locked Loops: Application to Coherent Receiver Design, Krieger Publishers, 1992.  F. M. Gardner, Phaselock Techniques, John Wiley & Sons, New York, 2005, 3rd edition.A. Chandra, NIT DGP – PLL 49/50
  • VLSI Systems Design 24/01/09 Thank You! aniruddha.chandra@ieee.org Questions???A. Chandra, NIT DGP – PLL 50/50