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  • 1. Deutsche Bank 2007 Technology Conference London Franki D’Hoore Director Investor Relations 14 September, 2007 <file name> / Slide 1 <version 00> <author>
  • 2. Safe Harbor “Safe Harbor” Statement under the U.S. Private Securities Litigation Reform Act of 1995: the matters discussed in this document may include forward-looking statements that are subject to risks and uncertainties including, but not limited to: economic conditions, product demand and semiconductor equipment industry capacity, worldwide demand and manufacturing capacity utilization for semiconductors (the principal product of our customer base), competitive products and pricing, manufacturing efficiencies, new product development, ability to enforce patents, the outcome of intellectual property litigation, availability of raw materials and critical manufacturing equipment, trade environment, and other risks indicated in the risk factors included in ASML’s Annual Report on Form 20-F and other filings with the U.S. Securities and Exchange Commission. / Slide 2
  • 3. ASML overview - The world’s leading provider of lithography systems for the semiconductor industry Ranked in the top 3 for Key facts Established: 1984 customer satisfaction for the 5th consecutive year Headquarters: Veldhoven, the Netherlands Market cap ~ €10 B Employees ~ 6,200 Customers: Serving 17 of the top 20 semi mfg. Equity Listing: Nasdaq and Euronext Leaders in Innovation Key financials ASML TWINSCAN € million 2005 2006 H1 2007 Market share (based on revenue) 57% 63% 66% Net sales 2,529 3,597 1895 Gross profit 974 1,462 777 EBIT 449 871 405 / Slide 3
  • 4. Industry growth drives Lithography tool consumption - NAND Flash fastest growing 60 Segment size: 20 Bio. US$ Exposure area 2006 [SI*10^9] 50 LOGIC 40 DRAM 30 MICRO ANALOG 20 NAND 10 NOR Other 0 0 5 10 15 20 25 30 CAGR Exposure Area 06-09 [%] Sources: ASML MCC, VLSI Research, iSuppli, SIA / Slide 4
  • 5. Customer Roadmaps drive Lithograph tool development 200 Half Pitch status : Logic = 65~90nm DRAM = 60~80nm NAND = 55~65nm 100 Half Pitch (nm) Logic 80 DRAM 60 40 NAND Flash Jan-04 Jan-06 Jan-08 Jan-00 Jan-02 Jan-10 Jan-12 / Slide 5
  • 6. ASML Lithography Roadmap 300mm λ Res. NA EUV 32nm 0.25 PPT 13 nm 40nm 0.25 ADT Decision point Hi Index <40nm >1.5 >1.5 NA? Next 40nm 1.35 ArFi XT:1900Gi 193 nm 45nm 1.20 XT:1700Fi 57nm XT:1450G 0.93 ArF 65nm XT:1400F 193 nm 70nm 0.85 XT:1250D 80nm 0.93 XT:1000H KrF 90nm XT:875F XT:875G 0.80 248 nm 110nm XT:870F XT:870G 130nm 0.70 XT:760F i-Line 220nm XT:450F XT:450G 0.65 365 nm 350nm XT:400F XT:400G 2006 2007 2008 2009 2010 2011 / Slide 6
  • 7. ASML TWINSCAN™ Product Specifications λ System Res. 300mm Throughput [WPH) & Overlay Roadmap Next <40nm >131 <6nm ArFi XT:1900 40nm G 131 , 6nm 193nm XT:1700i 45nm F 122 , 7nm XT:1450 57nm G 145 , 6nm ArF XT:1400 65nm F 133 , 6nm 193nm XT:1250 70nm D 120 , 8nm Continuous Improvement XT:1000 80nm H 165 , 6nm KrF XT:875 90nm F 135 , 8nm G 150 , 6nm 248nm XT:870 110nm F 135 , 8nm G 150 , 6nm XT:760 130nm F 130 , 12nm XT:450 220nm F 131 ,12nm G 141 ,12nm i-Line XT:400 350nm F 135 ,25nm G 149 ,25nm 365nm 2006 2007 2008 2009 2010 2011 Year / Slide 7
  • 8. ASML roadmap enables shrink for Logic, DRAM, and NAND flash at time required 200 Resolution/half pitch “Shrink” [nm] Logic Litho technology k1=0.4 DRAM will allow Logic to shrink 100 AT:850 NAND 80 AT:1200 k1=0.27 To enable XT:1400 60 continued R&D shrink for XT:1700i memory: EUV is XT:1900i needed, Double 40 ASML Product Patterning to XT:1450 Introduction R&D bridge gap until Double Patterning EUV mature 00 01 02 03 04 05 06 07 08 09 10 11 12 Year Source: Various customers, dates determine production start/qualification / Slide 8
  • 9. Technology in Time helps grow market share ASML market share (revenue) – Nearly tripled in 10 years Immersion 12” & ArF 80% KrF & Step & Scan 8” & i-line 60% 6” & early i-line 40% 20% 0% 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 03 04 05 06 1984 2006 Perkin Elmer Canon 16% Canon GCA ASML Nikon 63% Ultratech 21% Eaton Nikon ASET Hitachi Total market: €4,800 million Total market: €463 million Source: SEMI, Gartner Dataquest / Slide 9
  • 10. Immersion - Leadership continues Over 50 systems shipped to date to all applications and geographies in the world 25 immersion machines in backlog valued at € 728 M Received repeat orders from major Japanese customers including multiple XT:1900i machines ASML plans to ship about 35 immersion machines in 2007 Backlog in value ArF Immersion ArF dry 37 % is 42% of backlog KrF 15% i-line 6% / Slide 10
  • 11. First TWINSCAN XT:1900i shipped on schedule early July First tool in the world capable of printing features below 40 nm in volume production / Slide 11
  • 12. Exposed wafers (x1000) 1000 1500 2000 2500 0 500 Jan-05 Feb-05 / Slide 12 Mar-05 Apr-05 May-05 Jun-05 cumulative Jul-05 Aug-05 Sep-05 Oct-05 Nov-05 Dec-05 Jan-06 Feb-06 Mar-06 Apr-06 May-06 Jun-06 Jul-06 Aug-06 Sep-06 Oct-06 Nov-06 Dec-06 Jan-07 Wafers exposed on ASML immersion equipment Feb-07 Mar-07 Over 2 Million wafers processed on ASML immersion systems with steep production ramp since April 2007 Apr-07 May-07 Jun-07
  • 13. The layout designers draw, is not quite what gets printed by scanners 180nm 130nm 90nm 65nm / Slide 13
  • 14. Why is this happening? Because the litho process is not an error-free transfer function H≠1 Mask-writing Wafer exposure Resist development Etch / Slide 14
  • 15. What can we do about it? Software compensation for the distortion ~1/H H … … … / Slide 15
  • 16. In practice… Silicon Image w/o correction Mask (no correction) Design Layout Mask Silicon Image with (with correction, RET/OPC or “RET/OPC”) / Slide 16
  • 17. What does Brion do? H≠1 Mask-writing Wafer exposure Resist development Etch Accurate mathematical model of “H” Simulated wafer, Designers drawing before you print anything / Slide 17
  • 18. With an accurate mathematical model of H, we can do two things: Brion’s Tachyon OPC+ product line i.e. Approximate 1/H Compensate on design Scanner tuning Compensate i.e. Find H’ so distortion is less on scanner and/or easier to compensate for / Slide 18
  • 19. Through accurate model, we can fine tune many system settings for optimum exposure of each device pattern, reticle & wafer Illuminator Illuminator Laser Laser Sigma Pupicom Bandwidth PSEs DOEs Dose Stages Stages Unicom Etc. Focus Tilt X Tilt Y Lens Lens Reticle height Synchronization NA Manipulators / Slide 19
  • 20. Synergies of owning the scanner and the litho model for scanner-tuning System setting ranges : Optimum system settings : NA range NA Illumination option/ranges standard & custom Illumination setting (standard, custom) DoseMapper correction range Focus, Dose settings etc. etc. Actual system data Lens heating characteristics Real time system optimisation : Aberration data Lens manipulator settings Stray light Exposure dose & DoseMapper offsets Laser bandwidth Focus & tilt by shot / wafer etc. Laser bandwidth Wafer metrology & exposure data: Alignment & wafer grid offsets / field/wafer Focus & Leveling & focus hot spot data Dose error, Laser data Other etc. / Slide 20
  • 21. The holy-grail of optimisation: today, only ASML can do this Non - Optimized Optimized Scanner (e.g. Illumination) Optimize both the scanner and the mask, together, as a unified Mask optimization problem Top-down photoresist / Slide 21
  • 22. With Brion, ASML now can… (1/2) Leverage a whole new dimension of possibilities for optimizing imaging performance (mask optimization, RET/OPC) as an integral part of its solution package Use an accurate model of the lithography process to tune the dozens of scanner knobs available so to further optimize imaging performance (scanner tuning) Through the two points above, enable faster shrink and higher yield for our customers / Slide 22
  • 23. With Brion, ASML now can… (2/2) Further secure the ArF roadmap until EUV is ready Prevent value-migration to EDA by capturing software solutions to printability Penetrate a new and growing market at the interface with EDA, capturing new value streams and enabling growth beyond “hardware” / Slide 23
  • 24. Lithography System costs will continue to rise 100 300mm 150mm 200mm Wafer Size Wafer Size Relative List Price Dual Stage 1.35 1.2 0.93 Step & Scan 10 Platform 0.8 Platform 0.7 Stepper 0.5 Aperture Aperture 0.6 Wavelength Wavelength 0.4 i-line KrF ArF ArFi EUV? 1 1985 1990 1995 2000 2005 2010 Year / Slide 24
  • 25. Average Selling Price (ASP) grows ArF volume ASML ASP new systems & ArFi 16 300mm & ArF 14 KrF & 12 Step & Scan million Euro 10 8 6 4 2 0 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 / Slide 25
  • 26. Are lithography systems becoming unaffordable? 10,000 150mm 200mm 300mm 1,000 Relative cost reduction Relative cost reduction (pixels/hour/MEuro) (pixels/hour/MEuro) = 60% // generation = 60% generation Relative shrink Relative shrink 100 increase (pixels/field) increase (pixels/field) = 100% // generation = 100% generation Relative price increase Relative price increase 10 = 40% // generation = 40% generation Relative productivity Relative productivity increase (mm2/hour) increase (mm2/hour) = 30% // generation = 30% generation 1 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 / Slide 26
  • 27. Lithography Affordability for Future Shrink 2.6 Relative System Cost 2.4 Relative System WPH Relative Performance 2.2 Relative Cost / Function / Hour 2.0 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 AT:1150C XT:1400E XT:1900i NEXTi EUVL Model 90nm 65nm 40nm 28* 22 Resolution 4GB 8GB 16GB 32GB 64GB NAND Flash 2003 2005 2007 2009 2011 Year * Double Patterning / Slide 27
  • 28. ASML Competitive Advantage 2.00 Pixels per Hour per Million Euro ASML ArF 1.75 Competition ArF ASML ArFi 1.50 Competition ArFi 1.25 1.00 0.75 0.50 0.25 0.00 2004 2005 2006 2007 2008 / Slide 28
  • 29. Summary Shrinking design rules have been the economical driver of the IC industry. Lithography remains the key enabler Providing the right product at the right time allows market share gains for ASML Shrinking design rules require increasingly more sophisticated lithography systems resulting in a steady growth in their cost and resulting ASP’s ASML insures that the increasing cost of advanced lithography systems remain acceptable by developing solutions that result in maximum usable shrink while driving increased productivity to ensure steady improvement in cost per function Future lithography technologies will likely ensure that the economics of shrink will remain attractive for at least several more generations / Slide 29
  • 30. Commitment / Slide 30