Simulation using model sim


Published on

1 Like
  • Be the first to comment

No Downloads
Total Views
On Slideshare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

Simulation using model sim

  1. 1. VHDL 360©<br />by: Amr Ali<br />
  2. 2. Copyrights<br />Copyright © 2010 to authors. All rights reserved<br />All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Amr Ali or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.<br />Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.<br />Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. <br />Product names and trademarks mentioned in this presentation belong to their respective owners.<br />VHDL 360 ©<br />2<br />
  3. 3. Objective<br />Using ModelSim to compile and simulate a given design unit<br />Skills gained:<br />Identify basic Simulator commands<br />VHDL 360 ©<br />3<br />
  4. 4. Outline<br />Command Line Simulation<br />Compile and Simulate<br />Add Signals to Wave<br />Applying Inputs<br />Interactive Simulation<br />VHDL 360 ©<br />4<br />
  5. 5. Command Line Simulation<br />Make sure Modelsim exists in the path by doing the following<br />Windows:<br />Start run -> cmd<br />In cmd window:<br />vsim -version<br />Linux:<br />In any shell:<br />vsim -version<br />VHDL 360 ©<br />5<br />
  6. 6. Command Line Simulation<br />Create VHDL file<br />Edit the file my_demo1.vhd<br />Insert the text and save<br />VHDL 360 ©<br />6<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />ENTITYandgateIS<br />port(a, b:instd_logic_vector(2downto0);<br /> c:outstd_logic_vector(2downto0));<br />ENDENTITY;<br />ARCHITECTUREbehavOFandgateIS<br />BEGIN<br /> c <= a and b;<br />ENDARCHITECTURE;<br />
  7. 7. Compile and Simulate<br />vlib work<br />vcom <VHDL files> <br />vsim <top level><br />VHDL 360 ©<br />7<br /><ul><li>vlib: creates a library to compile and simulate the code with
  8. 8. vcom: compiles VHDL files, the files should be ordered in a hierarchal way [leaf level first then top]
  9. 9. vsim: starts the simulator to simulate the top level module</li></li></ul><li>Add signals to Wave<br />RMB on any signal in the Objects window  Add  to Wave  signals in Region<br />Now start applying inputs and monitor outputs<br />VHDL 360 ©<br />8<br />
  10. 10. Applying Inputs<br />RMB on input port  force<br />VHDL 360 ©<br />9<br /><ul><li>In the “value” field, insert an appropriate value OK
  11. 11. Apply inputs to other inputs</li></li></ul><li>Run Simulation<br />Press run button<br />Monitor the output<br />VHDL 360 ©<br />10<br />
  12. 12. Make Files<br />On Unix:<br />If you changed the code you will have to recompile the design files again.<br />A make file is used to do repetitive compilation and simulation tasks; “Make” knows which files have been edited and automatically compiles only changed files.<br />ModelSim offers a simple way to automatically generate a Makefile for your design hierarchy.<br />vmake work > Makefile<br />To recompile code at anytime just type<br /> make<br />VHDL 360 ©<br />11<br />
  13. 13. Interactive Simulation<br />File  new project<br />Insert project name and location; leave other fields with defaults<br />VHDL 360 ©<br />12<br />
  14. 14. Interactive Simulation<br />In “Add items to the project” window choose “Create new file”<br />Insert file name<br />Make sure to select VHDL<br />VHDL 360 ©<br />13<br />
  15. 15. Interactive Simulation<br />Create VHDL file<br />Edit the file my_demo1.vhd<br />Insert the text and save<br />VHDL 360 ©<br />14<br />LIBRARYieee;<br />USEieee.std_logic_1164.all;<br />ENTITYandgateIS<br />port(a, b:instd_logic_vector(2downto0);<br /> c:outstd_logic_vector(2downto0));<br />ENDENTITY;<br />ARCHITECTUREbehavOFandgateIS<br />BEGIN<br /> c <= a and b;<br />ENDARCHITECTURE;<br />
  16. 16. Compile VHDL files<br />Select the file  RMB  compile selected<br />VHDL 360 ©<br />15<br />
  17. 17. Simulation<br />Simulate menu  Start Simulation<br />Expand work library and select andgateOK<br />VHDL 360 ©<br />16<br />
  18. 18. Contacts<br />You can contact us at:<br /><br />VHDL 360 ©<br />17<br />
  1. A particular slide catching your eye?

    Clipping is a handy way to collect important slides you want to go back to later.