Post Place and Route Simulion

VHDL 360©
by: Amr Ali

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Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.
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VHDL 360 ©
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Objective
Post place and route simulation using Xilinx ISE
Skills gained:
Knowledge of post place and route simulation flow
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Outline
Compiling simulation libraries
Post PAR simulation
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Compile Simulation Libraries
FPGA simulation libraries should be compiled before doing post synthesis or post PAR simulation
FPGA simulation libraries contains definition of logic components used in the simulation model
Compiled FPGA simulation libraries are independent on the simulated design and can be used as much as the FPGA family used in implementation isn't changed
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Select the project node
Right click on “Compile HDL simulation libraries” -> “process properties”
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Set language to the one used in generating the design simulation model (will speak about it later)
You may need to set the language to “all” if the simulator requires VHDL and Verilog libraries
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VHDL 360 ©

Now run “Compile HDL simulation libraries”
Wait for compilation to finish
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Post PAR Simulation
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Generating Simulation Model
Select top level entity
Right click on “Generate Place and Route Simulation Model” -> “process properties”
Change “Simulation Model Target” to “VHDL”

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Post Place and Route Simulion

by amraldo on Feb 25, 2011

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Post Place and Route Simulion — Presentation Transcript