Post Place and Route Simulion
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Post Place and Route Simulion Presentation Transcript

  • 1. VHDL 360©
    by: Amr Ali
  • 2. Copyrights
    Copyright © 2010/2011 to authors. All rights reserved
    All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Amr Ali or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.
    Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.
    Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact.
    Product names and trademarks mentioned in this presentation belong to their respective owners.
    VHDL 360 ©
    2
  • 3. Objective
    Post place and route simulation using Xilinx ISE
    Skills gained:
    Knowledge of post place and route simulation flow
    VHDL 360 ©
    3
  • 4. Outline
    Compiling simulation libraries
    Post PAR simulation
    VHDL 360 ©
    4
  • 5. Compile Simulation Libraries
    FPGA simulation libraries should be compiled before doing post synthesis or post PAR simulation
    FPGA simulation libraries contains definition of logic components used in the simulation model
    Compiled FPGA simulation libraries are independent on the simulated design and can be used as much as the FPGA family used in implementation isn't changed
    VHDL 360 ©
    5
  • 6. Compile Simulation Libraries
    Select the project node
    Right click on “Compile HDL simulation libraries” -> “process properties”
    VHDL 360 ©
    6
  • 7. Compile Simulation Libraries
    Set language to the one used in generating the design simulation model (will speak about it later)
    You may need to set the language to “all” if the simulator requires VHDL and Verilog libraries
    7
    VHDL 360 ©
  • 8. Compile Simulation Libraries
    Now run “Compile HDL simulation libraries”
    Wait for compilation to finish
    8
    VHDL 360 ©
  • 9. Post PAR Simulation
    VHDL 360 ©
    9
    Generating Simulation Model
    Select top level entity
    Right click on “Generate Place and Route Simulation Model” -> “process properties”
    Change “Simulation Model Target” to “VHDL”
  • 10. Post PAR Simulation
    Right click on “Generate Place and Route Simulation Model” -> “Run”
    10
    VHDL 360 ©
  • 11. Post PAR Simulation
    Select “Sources for”
    “Post-Route Simulation”
    OR
    11
    VHDL 360 ©
  • 12. Post PAR Simulation
    Select top level entity
    Run “Simulate Post-Place & Route Model”
    12
    VHDL 360 ©
  • 13. Contacts
    You can contact us at:
    http://www.embedded-tips.blogspot.com/
    VHDL 360 ©
    13