Introduction to STM32
Course Objective <ul><li>After completing this course, you will answer: </li></ul><ul><ul><li>What is ARM Cortex Processor...
Course Notes <ul><li>Set your cell phone to vibrate. </li></ul><ul><li>I assume you know computer architecture. </li></ul>...
Course References <ul><li>The Definitive Guide to the ARM Cortex-M3, 2 nd  Edition </li></ul><ul><li>www.arm.com </li></ul...
Course Outline <ul><li>Introduction </li></ul><ul><li>Cortex Overview </li></ul><ul><li>CMSIS </li></ul><ul><li>STM32 Syst...
Course Outline <ul><li>Introduction </li></ul><ul><li>Cortex Overview </li></ul><ul><li>CMSIS </li></ul><ul><li>STM32 Syst...
CPU, Processor, and SoC Amr Ali Abdel-Naby@2011 Introduction to STM32
About ARM <ul><li>ARM = Advanced/Acorn RISC Machine </li></ul><ul><li>Founded in 1990 </li></ul><ul><li>CPU IPs, physical ...
ARM Customers <ul><li>IDMs/IC vendors like: </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
ARM Overview Amr Ali Abdel-Naby@2011 Introduction to STM32
ARM by Architecture Amr Ali Abdel-Naby@2011 Introduction to STM32
ARM Application Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
ARM Embedded Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
ARM Secure/Specialities Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
About ST Microelectronics <ul><li>Merge of SG Microelectronica and Thomson Semiconductors </li></ul><ul><li>Founded in 198...
Course Outline <ul><li>Introduction </li></ul><ul><li>Cortex Overview </li></ul><ul><li>CMSIS </li></ul><ul><li>STM32 Syst...
What is Cortex? <ul><li>Next generation ARM Processor </li></ul><ul><li>Consists of: </li></ul><ul><ul><li>Classic CPU(s) ...
Cortex CPU <ul><li>32-bit RISC </li></ul><ul><li>16 registers </li></ul><ul><li>3 stages pipeline with branch prediction <...
CPU Operating Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
Thumb-2 Instruction Set <ul><li>32-bit performance with 16-bit code density </li></ul><ul><li>Need for non ANSI-C is minim...
Memory Map Amr Ali Abdel-Naby@2011 Introduction to STM32
Unaligned Memory Access Amr Ali Abdel-Naby@2011 Introduction to STM32
Bit Banding Amr Ali Abdel-Naby@2011 Introduction to STM32
Buses <ul><li>Code and Data buses </li></ul><ul><ul><li>Harvard architecture </li></ul></ul><ul><li>System bus </li></ul><...
System Timer <ul><li>24-bit down counter </li></ul><ul><ul><li>Auto-reload and end of count interrupt </li></ul></ul><ul><...
Nested Vector Interrupt Controller <ul><li>Very low deterministic interrupt latency </li></ul><ul><li>Nested interrupts </...
NVIC Exception Entry and Exit Amr Ali Abdel-Naby@2011 Introduction to STM32
Handling Multiple Interrupts <ul><li>A HPI preempts a LPI (12 cycles needed) </li></ul><ul><li>6 cycles are needed to fetc...
NVIC Configure and Usage <ul><li>Done on 3 steps: </li></ul><ul><ul><li>Configure the exception vector table </li></ul></u...
Configure the Exception Vector Table Amr Ali Abdel-Naby@2011 Introduction to STM32
Configure the NVIC Registers <ul><li>Set the priority of the interrupt </li></ul><ul><li>Enable the interrupt source </li>...
Power Modes <ul><li>CPU enters sleep mode either by: </li></ul><ul><ul><li>WFI </li></ul></ul><ul><ul><ul><li>Wakes by an ...
CoreSight Debug Support Amr Ali Abdel-Naby@2011 Introduction to STM32
Course Outline <ul><li>Introduction </li></ul><ul><li>Cortex Overview </li></ul><ul><li>CMSIS </li></ul><ul><li>STM32 Syst...
What is CMSIS? <ul><li>Cortex Microcontroller Software Interface Standard </li></ul><ul><li>A vendor independent software ...
CMSIS Structure Amr Ali Abdel-Naby@2011 Introduction to STM32
File Structure <ul><li>core_cm3.h </li></ul><ul><ul><li>Cortex M3 global declarations </li></ul></ul><ul><li>core_cm3.c </...
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Introduction to stm32-part1

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  • * 07/16/96 * ##
  • ISA: Instruction Set Architecture VFP: Vector Floating Point Jazelle: Extension to run Java Byte Code on ARM machines ARM ISA: 32-bit instructions Thumb ISA: 16-bit instructions Thumb-2 ISA: ARM + Thumb TrustZone: Security Extensions SIMD: Single Instruction Multiple Data NEON: Advanced SIMD Virtualization: Hardware Virtualization NVIC: Nested Vector Interrupt Controller WIC:Wakeup Interrupt Controller * 07/16/96 * ##
  • They can execute complex operating systems. Phones, notebooks, PDAs, DTVs, set-top boxes… * 07/16/96 * ##
  • Suitable for real-time behavior of power-sensitive applications Control systems, automotive, white goods… * 07/16/96 * ##
  • SIMs, smart cards, electronic IDs, electronic payments… * 07/16/96 * ##
  • N: Negative Z: Zero C: Carry V: Overflow Q: Saturated minimum/maximum result T: Thumb mode ICI: Interrupt continuable instruction  To support deterministic interrupt latency for multi-cycle instructions IT: If then  To support conditional execution (execute or NOP) T: Thumb mode  Always set to 1 ISR #: NVIC is integrated with core * 07/16/96 * ##
  • Flat mode: Out of reset mode = Thread mode + Privileged Operations + Main Stack * 07/16/96 * ##
  • DMIPS = Dhrystone MIPS, free benchmark to compare CPU perfromance * 07/16/96 * ##
  • Aligned access (left, classical ARM) allows efficient access of variables without need of software libraries support but can waste up to 25% of variable space. Unaligned access (right, Cortex ARM) makes more efficient use of memory. Cortex supports both modes by hardware! * 07/16/96 * ##
  • Bit manipulation without bit banding (left, classical ARM) needed a read, modify, write operations to change a single bit Bit banding manipulation (right, Cortex ARM) uses alias region to add * 07/16/96 * ##
  • * 07/16/96 * ##
  • Starts at the bottom of the address range at 0x00000004. Address 0x0000000 is used to store initial SP. The exception vector table stores addresses rather than instructions. The 1 st 15 are for the ones used by the Cortex core itself. * 07/16/96 * ##
  • WFI: Wait for interrupt WFE: Wait for event * 07/16/96 * ##
  • JTAG (classical ARM) only worked when CPU is halted. HW breakpoints are only two. Real-time trace can be supported using an Embedded Trace Module (ETM) at extra cost. CoreSight (Cortex ARM) can work with old JTAG interfaces! Hardware tracers built-in. Up to 8 HW breakpoints. Can debug in sleep modes. Synchronize CPU with timers when halted. * 07/16/96 * ##
  • * 07/16/96 * ##
  • CPAL is implemented by ARM to access the CPU HW MWAL defined by ARM but adapted by silicon vendors to access the SoC devices. It is not implemented yet. DPAL similar to CAPL but defined and implemented by silicon vendors. They use CAPL internally. * 07/16/96 * ##
  • Transcript of "Introduction to stm32-part1"

    1. 1. Introduction to STM32
    2. 2. Course Objective <ul><li>After completing this course, you will answer: </li></ul><ul><ul><li>What is ARM Cortex Processor? </li></ul></ul><ul><ul><li>What is the STM32 SoC? </li></ul></ul><ul><ul><li>What are STM32 building blocks? </li></ul></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    3. 3. Course Notes <ul><li>Set your cell phone to vibrate. </li></ul><ul><li>I assume you know computer architecture. </li></ul><ul><li>Ask any time. </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    4. 4. Course References <ul><li>The Definitive Guide to the ARM Cortex-M3, 2 nd Edition </li></ul><ul><li>www.arm.com </li></ul><ul><li>www.st.com/stm32 </li></ul><ul><li>www.doulos.com </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    5. 5. Course Outline <ul><li>Introduction </li></ul><ul><li>Cortex Overview </li></ul><ul><li>CMSIS </li></ul><ul><li>STM32 System Architecture </li></ul><ul><li>Peripherals </li></ul><ul><li>Low Power Operation </li></ul><ul><li>Safety Features </li></ul><ul><li>The Flash Module </li></ul><ul><li>Development Tools </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    6. 6. Course Outline <ul><li>Introduction </li></ul><ul><li>Cortex Overview </li></ul><ul><li>CMSIS </li></ul><ul><li>STM32 System Architecture </li></ul><ul><li>Peripherals </li></ul><ul><li>Low Power Operation </li></ul><ul><li>Safety Features </li></ul><ul><li>The Flash Module </li></ul><ul><li>Development Tools </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    7. 7. CPU, Processor, and SoC Amr Ali Abdel-Naby@2011 Introduction to STM32
    8. 8. About ARM <ul><li>ARM = Advanced/Acorn RISC Machine </li></ul><ul><li>Founded in 1990 </li></ul><ul><li>CPU IPs, physical IPs, compilers, SoC infrastructure… </li></ul><ul><li>Dominates 75% of embedded market </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    9. 9. ARM Customers <ul><li>IDMs/IC vendors like: </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    10. 10. ARM Overview Amr Ali Abdel-Naby@2011 Introduction to STM32
    11. 11. ARM by Architecture Amr Ali Abdel-Naby@2011 Introduction to STM32
    12. 12. ARM Application Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
    13. 13. ARM Embedded Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
    14. 14. ARM Secure/Specialities Processors Amr Ali Abdel-Naby@2011 Introduction to STM32
    15. 15. About ST Microelectronics <ul><li>Merge of SG Microelectronica and Thomson Semiconductors </li></ul><ul><li>Founded in 1987 </li></ul><ul><li>ICs, smart cards, microcontrollers… </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    16. 16. Course Outline <ul><li>Introduction </li></ul><ul><li>Cortex Overview </li></ul><ul><li>CMSIS </li></ul><ul><li>STM32 System Architecture </li></ul><ul><li>Peripherals </li></ul><ul><li>Low Power Operation </li></ul><ul><li>Safety Features </li></ul><ul><li>The Flash Module </li></ul><ul><li>Development Tools </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    17. 17. What is Cortex? <ul><li>Next generation ARM Processor </li></ul><ul><li>Consists of: </li></ul><ul><ul><li>Classic CPU(s) </li></ul></ul><ul><ul><li>System peripherals </li></ul></ul><ul><li>3 series: </li></ul><ul><ul><li>A series: for complex applications and OS </li></ul></ul><ul><ul><li>R series: for real-time systems </li></ul></ul><ul><ul><li>M series: optimized for cost/power sensitive systems </li></ul></ul><ul><li>15 performance levels: 0 lowest </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    18. 18. Cortex CPU <ul><li>32-bit RISC </li></ul><ul><li>16 registers </li></ul><ul><li>3 stages pipeline with branch prediction </li></ul><ul><li>Load-store architecture </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    19. 19. CPU Operating Modes Amr Ali Abdel-Naby@2011 Introduction to STM32
    20. 20. Thumb-2 Instruction Set <ul><li>32-bit performance with 16-bit code density </li></ul><ul><li>Need for non ANSI-C is minimum </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    21. 21. Memory Map Amr Ali Abdel-Naby@2011 Introduction to STM32
    22. 22. Unaligned Memory Access Amr Ali Abdel-Naby@2011 Introduction to STM32
    23. 23. Bit Banding Amr Ali Abdel-Naby@2011 Introduction to STM32
    24. 24. Buses <ul><li>Code and Data buses </li></ul><ul><ul><li>Harvard architecture </li></ul></ul><ul><li>System bus </li></ul><ul><ul><li>Cortex control space </li></ul></ul><ul><li>Private peripheral bus </li></ul><ul><ul><li>On-chip debug system </li></ul></ul><ul><li>Bus matrix </li></ul><ul><ul><li>Connects the 1 st 3 buses to the external world </li></ul></ul><ul><ul><li>Bus arbiters </li></ul></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    25. 25. System Timer <ul><li>24-bit down counter </li></ul><ul><ul><li>Auto-reload and end of count interrupt </li></ul></ul><ul><li>Provide timer tick for OS </li></ul><ul><li>Has 3 registers: </li></ul><ul><ul><li>Control & status </li></ul></ul><ul><ul><ul><li>Enable, select clock source… </li></ul></ul></ul><ul><ul><li>Reload value </li></ul></ul><ul><ul><li>Current value </li></ul></ul><ul><ul><li>Both reload and current registers should be initialized with period </li></ul></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    26. 26. Nested Vector Interrupt Controller <ul><li>Very low deterministic interrupt latency </li></ul><ul><li>Nested interrupts </li></ul><ul><li>ANSI C programmed </li></ul><ul><li>Configurable by manufacture to the needed number of interrupts </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    27. 27. NVIC Exception Entry and Exit Amr Ali Abdel-Naby@2011 Introduction to STM32
    28. 28. Handling Multiple Interrupts <ul><li>A HPI preempts a LPI (12 cycles needed) </li></ul><ul><li>6 cycles are needed to fetch new ISR address </li></ul><ul><li>Tail chaining ensures minimum delay between interrupts in 3 cases: </li></ul><ul><ul><li>2 interrupts raised at same time (6 cycles needed) </li></ul></ul><ul><ul><li>LPI occurs at HPI exit (7 to 18 cycles needed) </li></ul></ul><ul><ul><li>HPI occurs during push of LPI (6 cycles needed from HPI occurrence) </li></ul></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    29. 29. NVIC Configure and Usage <ul><li>Done on 3 steps: </li></ul><ul><ul><li>Configure the exception vector table </li></ul></ul><ul><ul><li>Configure the NVIC registers </li></ul></ul><ul><ul><li>Configure the peripherals </li></ul></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    30. 30. Configure the Exception Vector Table Amr Ali Abdel-Naby@2011 Introduction to STM32
    31. 31. Configure the NVIC Registers <ul><li>Set the priority of the interrupt </li></ul><ul><li>Enable the interrupt source </li></ul><ul><li>Internal exceptions are configured using system control and system priority </li></ul><ul><li>User exceptions are configured using IRQ registers </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    32. 32. Power Modes <ul><li>CPU enters sleep mode either by: </li></ul><ul><ul><li>WFI </li></ul></ul><ul><ul><ul><li>Wakes by an interrupt </li></ul></ul></ul><ul><ul><ul><li>Executes an ISR </li></ul></ul></ul><ul><ul><li>WFE </li></ul></ul><ul><ul><ul><li>Wakes by an external event line </li></ul></ul></ul><ul><li>SLEEPONEXT: Puts CPU back in sleep mode after ISR </li></ul><ul><li>SEVONPEND: An ISR even if disabled can generate an event </li></ul><ul><li>SLEEPDEEP: Halts peripherals as well like PLL </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    33. 33. CoreSight Debug Support Amr Ali Abdel-Naby@2011 Introduction to STM32
    34. 34. Course Outline <ul><li>Introduction </li></ul><ul><li>Cortex Overview </li></ul><ul><li>CMSIS </li></ul><ul><li>STM32 System Architecture </li></ul><ul><li>Peripherals </li></ul><ul><li>Low Power Operation </li></ul><ul><li>Safety Features </li></ul><ul><li>The Flash Module </li></ul><ul><li>Development Tools </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    35. 35. What is CMSIS? <ul><li>Cortex Microcontroller Software Interface Standard </li></ul><ul><li>A vendor independent software layer </li></ul><ul><ul><li>This will ease porting and reusing of software </li></ul></ul><ul><li>MISRA compliant </li></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32
    36. 36. CMSIS Structure Amr Ali Abdel-Naby@2011 Introduction to STM32
    37. 37. File Structure <ul><li>core_cm3.h </li></ul><ul><ul><li>Cortex M3 global declarations </li></ul></ul><ul><li>core_cm3.c </li></ul><ul><ul><li>Cortex M3 global definitions </li></ul></ul><ul><li>core_cm3.x are tool independent. </li></ul><ul><li><device>.h </li></ul><ul><ul><li>To be included in application software </li></ul></ul><ul><li>system_<device>.h </li></ul><ul><ul><li>Device specific declarations </li></ul></ul><ul><li>system_<device>.c </li></ul><ul><ul><li>Device specific definitions </li></ul></ul>Amr Ali Abdel-Naby@2011 Introduction to STM32

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