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Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
Verilog Pli
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Verilog Pli

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    • 1. Introduction to Verilog PLI By : Sibin P. Thomas
    • 2. <ul><li>What is the Verilog PLI? </li></ul><ul><li>Where is it useful/used? </li></ul><ul><li>Fundamentals of Verilog PLI </li></ul><ul><li>How to work with Verilog PLI? </li></ul>A genda
    • 3. W hat is the Verilog PLI?
    • 4. <ul><li>PLI ≡ Programming Language Interface </li></ul><ul><li>The PLI of Verilog HDL is a mechanism to provide an Application Programming Interface (API) to Verilog HDL. </li></ul><ul><li>Essentially a mechanism to invoke a C function from Verilog code. </li></ul><ul><li>It also provides mechanism to access internal databases of the simulator from the C program. </li></ul><ul><li>C function invoked by Verilog through a user provided system call like any other system call $finish, $display etc. </li></ul><ul><li>We can over-ride any pre-existing system call through PLI! </li></ul>
    • 5. W here is it useful/used?
    • 6. <ul><li>We basically use it to do what is not possible through Verilog constructs – </li></ul><ul><li>Reading a register from file </li></ul><ul><li>Instance name of the parent of the current module in the design hierarchy. </li></ul><ul><li>Provide a user interface </li></ul><ul><li>… </li></ul>Where is it useful/used?
    • 7. <ul><li>Writing BFMs </li></ul><ul><li>Writing Test Benches </li></ul><ul><li>Co – Verification </li></ul><ul><li>Getting design information </li></ul><ul><li>Code Coverage applications </li></ul><ul><li>… </li></ul>Where is it useful/used?
    • 8. F undamentals of Verilog PLI
    • 9. <ul><li>Each system call is associated with 4 types of functions </li></ul><ul><li>Checktf </li></ul><ul><ul><li>Encountered during parsing or compiling </li></ul></ul><ul><li>Calltf </li></ul><ul><ul><li>each time the associated user-defined system task is called in verilog </li></ul></ul><ul><li>Sizetf </li></ul><ul><ul><li>early in the process, prior to a complete instantiation of the design. </li></ul></ul><ul><li>Misctf </li></ul><ul><ul><li>For miscellaneous reasons! Like reason_finish etc </li></ul></ul>F undamentals of Verilog PLI
    • 10. Different PLI libraries <ul><li>TF library </li></ul><ul><li>ACC library </li></ul><ul><li>VPI library </li></ul>
    • 11. TF library <ul><li>Advantages – </li></ul><ul><ul><li>Oldest PLI library, hence one can find more documentation and support for these routines. </li></ul></ul><ul><ul><li>Fairly simple and easy to understand; i.e. a shorter learning curve. </li></ul></ul><ul><ul><li>VCS is often 2x to 5x faster when only the TF library used. </li></ul></ul><ul><li>Limitations – </li></ul><ul><ul><li>Cannot analyze Verilog&apos;s internal simulation data structures. </li></ul></ul><ul><ul><li>Non Portable between different simulators. </li></ul></ul><ul><ul><li>New Verilog-2001 (IEEE 1364-2001) features are not supported. </li></ul></ul>
    • 12. ACC library <ul><li>Advantages – </li></ul><ul><ul><li>Allows software to actually occupy the driving seat and control the Simulation by allowing access to Verilog constructs. </li></ul></ul><ul><ul><li>Useful for a wider range of applications. </li></ul></ul><ul><li>Limitations – </li></ul><ul><ul><li>Cannot access RTL and test bench portions of Verilog HDL. </li></ul></ul><ul><ul><li>Cannot access memory arrays </li></ul></ul><ul><ul><li>Non Portable. </li></ul></ul>
    • 13. VPI library <ul><li>Advantages - </li></ul><ul><ul><li>Consists of just 37 routines compared to over a 100 in each of TF/ACC libraries. </li></ul></ul><ul><ul><li>Full access to structural, RTL and test bench constructs. </li></ul></ul><ul><ul><li>Portable to all Simulators and also 64-bit operating systems. </li></ul></ul><ul><ul><li>All the new features in Verilog-2001 are supported by the VPI library of the PLI. </li></ul></ul><ul><li>Limitations – </li></ul><ul><ul><li>Cannot be optimized as efficiently as TF library. </li></ul></ul><ul><ul><li>Since it is the latest in the family of PLI libraries the amount of help and support one would find for deploying this library is relatively lesser. </li></ul></ul>
    • 14. Integrating the C files with the Verilog files <ul><li>Static linking as in VCS </li></ul><ul><li>Dynamic linking as in VerilogXL, ModelSim etc. </li></ul>
    • 15. VCS style <ul><li>$hello call=hello_calltf misc=hello_misctf </li></ul><ul><li>vcs -P pli.tab my_verilog_file.v my_c_file.c </li></ul>
    • 16. Modelsim/Verilog XL <ul><li>s_tfcell veriusertfs[] = { </li></ul><ul><li>/*** </li></ul><ul><li>Template for an entry: </li></ul><ul><li>{ usertask|userfunction, data, checktf(), sizetf(), calltf(), misctf*/ </li></ul><ul><li>{usertask, 0, 0, 0, hello_calltf, hello_misctf, &amp;quot;$hello&amp;quot;}, </li></ul><ul><li>{0} /* last entry must be 0 */ </li></ul><ul><li>}; </li></ul>
    • 17. H ow to work with Verilog PLI?
    • 18. Imagination Action Joy

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