- While latches can present an intermediate voltage at the outputs, FF just present an non-deterministic delay (the chance of having intermediate voltage is very low thanks to the inverters asymmetry).
Here we allow one cycle for settling
This is easy to chart with Excel or similar tool. You can draw your own if you need to change any of the parameters. If you can decide how much MTBF you want, you can find out how long S should be. Alternative formats of drawing the data were published by Xilinx in 2002 (reference below). Note that if F C remains the same but we consider the slow corner (tau and W 50% higher, say tau=100ps and W=200ps), the MTBF values are smaller. But there is also a simpler way of approaching this.
FO4 gate delay depends (roughly) linearly or quadratically on voltage. But MTBF depends exponentially on delay, hence exponentially on voltage !!!
Transcript
1.
Synchronization Issues in Multiple-Clock Domain Designs Reuven Dobkin vSync Circuits ltd. www.vsyncc.com May 4, 2010
The speed of each module may change over time for power reduction
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Taxonomy of Multiple Clock Domains R. Dobkin, R. Ginosar, "Fast Universal Synchronizers," PATMOS, 2008 0 drifts Multi-synchronous Asynchronous f d > Periodic f d < Varies Plesiochronous 0 c Mesochronous 0 0 Synchronous f Class
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: Recent findings (1) S. Beer, R. Dobkin, R. Ginosar, A. Kolodny, "The Devolution of Synchronizers," Proc. of ASYNC, 2010. We thank our partner GiDEL for supporting this research. We also thank Freescale Semiconductor for their support.
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: Recent findings (2) We thank our partner GiDEL for supporting this research. We also thank Freescale Semiconductor for their support. S. Beer, R. Dobkin, R. Ginosar, A. Kolodny, "The Devolution of Synchronizers," Proc. of ASYNC, 2010.
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