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Synopsys track c Synopsys track c Presentation Transcript

  • The Nanometer Challenges An EDA Vendor Perspective Marco Casale-Rossi Synopsys, Inc. 1
  • Dr. Gordon E. Moore’s Law Number of Transistors Doubles Every New Technology Node; Area & Cost Remain the Same S =√ 0.5 = ~0.7 The Scaling Factor “The complexity for minimum component costs has Number of increased at a rate of roughly a factor of two per year ... Certainly over the short term this rate can be Transistors = 2X expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more Area & Cost = 1X uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.” Source: G.E. Moore, Fairchild, Electronic Magazine 1965 2
  • The Nanometer Rush From 90 to 32 Nanometers (in Dual Core Processors) 90 nanometers 65 nanometers 45 nanometers 32 nanometers 206 mm2 143 mm2 107 mm2 81 mm2 230M transistors 291M transistors 410M transistors 382M transistors 3.2GHz 3.0GHz 3.4GHz 3.5GHz TDP = 130W TDP = 80W TDP = 80W TDP = 73W (1) Gate Density Gate Density Gate Density Gate Density 90 = 1X 90/65 1.82X 65/45 1.88X 45/32 1.23X Clock Rate Clock Rate Clock Rate Clock Rate 90 = 1X 90/65 0.94X 65/45 1.13X 45/32 1.03X TDP @ 3.0GHz TDP @ 3.0GHz TDP @ 3.0GHz TDP @ 3.0GHz 90 = 1X 90/65 0.61X 65/45 1X 45/32 0.91X(1) 1. TDP figures include the graphics & IMC die : 45 nanometers, 177M transistors, 114mm2 Source: M.Bohr, Intel, IDF 2008; www.intel.com, 2010 3 Note: These Examples Are for Illustration Purposes Only
  • Where Do We Stand ? Well,… 32/28 Nanometers Is Approximately the 23rd Technology Node Since 1959 M(0) M(1) … M(8) M(9) 100µ 70µ … 6µ 4.5µ M(10) M(11) M(12) M(13) M(14) 3µ 2µ 1.5µ 1µ 700 M(15) M(16) M(17) M(18) M(19) 500 350 250 180 130 M(20) M(21) M(22) M(23) … 90 65 45/40 32/28 … Source: R.N. Noyce, Fairchild 1959 4
  • The Nanometer Rush Let’s Draw Some Conclusions… • Clearly two phases : • Exponential down to 90 nanometers • Asymptotic thereafter ? • Increasing power density is the issue • Performance or power, hardly both 5
  • The Nanometer Challenges (I) Top Issues to Look at (1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate Source: ITRS 2009; NVIDIA 2009; ASML 2010 6
  • The Nanometer Challenges (II) Top Issues to Look at Source: ITRS 2009; Synopsys Research 2010 7
  • The Complexity Challenge Sheer Complexity Remains the #1 Challenge ! 1 5 2 6 3 4 STi5500 (1996) STi7200 (2006) 350 nanometers 65 nanometers 96mm2 80mm2 4M transistors 130M transistors 5W 5W Source: M. Taliercio, STMicroelectronics 2001; L. Bosson, STMicroelectronics 2006 8 Note: These Examples Are for Illustration Purposes Only
  • The Complexity Challenge Computational Complexity Exceeds the Pace of Moore’s Law Source: C.A. Malachowsky, Co-Founder, NVIDIA, EDPS 2009 9
  • The Lithography Challenge New Equipment Is Badly Needed ! Interim Solution : Double Patterning (DPT) Source: M. van den Brink, ASML 2010 10
  • The Lithography Challenge DPT Changes the Rules of the Game Source J. Finders, ASML, Research Review 2008 11
  • The Lithography Challenge Interconnect RC Delay A 2003 Estimate… A 2010 data point… @ 32 Nanometers Buffers ≈ 30% of Instances Source: P. Saxena, Intel, IDPS 2003; Synopsys Research 2010 12
  • The Variability Challenge Atomic Uncertainties in Dimensions and Dopants Lead to Increasing Power & Timing Variability Uniform Distribution, 130 Atoms Non Uniform Distribution, 130 Atoms LEFF = 30nm, VTH = 0.78V LEFF = 30nm, VTH = 0.56V Source: C. Kim, University of Minnesota, DAC 2007 13
  • The Variability Challenge Random Vs. Systematic Variations Courtesy of Prof. J. Rabaey, UCB, DATE 2009 14
  • The Power Challenge 50 to 100 Cores Won’t Be Uncommon • Intel’s terascale research processor • 80 * 21 “power islands” • Standby VDD & MTCMOS 2X to 5X leakage power reduction per core Polaris 21 “power islands” (not all shown) Source: J. Held, Intel, HPEC 2007 15
  • The Power Challenge Temperature-Awareness Source: P. Gelsinger, Intel, DAC 2004 16
  • The Power Challenge Complex, Multiple Scenarios Must Be Accounted for Power Does Impact Reliability Voltage drop in the 1st mode… …Voltage drop in the nth mode 17
  • The Reliability Challenge Aircrafts, Cars, Helicopters,… Everything Is Immersed in Mutually Interefering Electromagnetic Fields Source: NASA HIRF Laboratory, 2009 18
  • The Test Challenge Cost of Test (Test Time) Is on the Rise… Again ? Source: P. Gelsinger, Intel, DAC 2004 19
  • The Test Challenge Design- and Manufacturing-Aware Test “The future depends on our Design ability to develop DFM, DFT, Manufacturing and TFM domains… Such D FM developments require that T FM experts of each domain learn how to seek potential T FD solutions of the problems D FT posed by the inherent progress of technology, outside of the their own Test domains.” Source: Prof. W. Maly, CMU, IEEE D&TC, 1996 20
  • The Integration Challenge “More of Moore” Requires “More than Moore” CMOS 45 nanometers, Active interposer, 25mm2, digital functions, CMOS 130 nanometers, 1V & 1.8V 32mm2, analog functions, 1.xV, 2.5V & 3.3V Source: L. Bonnot, STMicroelectronics, D43D 2009 21
  • The Integration Challenge “More of Moore” Requires “More than Moore” CMOS 45 nanometers, Active interposer, 25mm2, digital functions, CMOS 130 nanometers, 1V & 1.8V 32mm2, analog functions, 1.xV, 2.5V & 3.3V Source: L. Bonnot, STMicroelectronics, D43D 2009 22
  • The Nanometer Challenges Some More Conclusions… • Sheer complexity is and will remain the biggest challenge at nanometer process nodes • Lithography cannot make it without design and EDA • Atomic variability – and uncertainty – is on the rise • Increasing power density is the issue • Interconnect resistance makes everything worse • Design for low power does impact reliability • Test time is on the rise, again ? • Design and EDA are increasingly critical to deal with the nanometer challenges ! 23
  • The Nanometer Solution Galaxy™ Implementation Platform Synthesis Signoff Place & Route 2009… 32/28 Nanometers “Convergence” 24
  • ™ Galaxy™ Implementation Platform All the Right Ingredients • Strong tools, methodolo- gies, and automated flows Synthesis • Comprehensive multicore solution • Convergence of RTL synthesis, physical imple- Signoff mentation, and sign-off • Broad portfolio of design for manufacturability, po- Place & Route wer, and test technologies • Tape-out proven with leading IDM, fabless, and foundry partners 25
  • ‫ָה‬ ‫ד‬ Tel Aviv, Israel May 4th, 2010 26