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    Bary pangrle   mentor track d Bary pangrle mentor track d Presentation Transcript

    • Low Power Keeps Getting Hotter Barry Pangrle, Ph.D. Solutions Architect Mentor Graphics Corporation Israel, May 4, 2010 © 2010 Mentor Graphics Corp. www.mentor.com
    • The Next 25 Minutes… • Purpose: – Update Information on Power-Efficient Design • Process: – Background – Trends Data – Q&A • Outcome: – Better Understanding of: • Where the Industry is Going • How it Affects You • How to Best Leverage the Design Process for Your Needs Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 2 www.mentor.com
    • Designers Facing More Green Requirements Created and runs the Energy Star A global consortium dedicated to Program in the U.S. among other developing and promoting energy programs for controlling efficiency for data centers and business environmental impact computing ecosystems Companies displaying The Green Fan logo Aims to reduce energy consumption in demonstrate that they are actively making worldwide ICT networks by a factor of a positive contribution to reducing CO2 1000 emissions Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 3 www.mentor.com
    • Power Impacts the Whole System HLS HLS TLM TLM Architectural Analysis Architectural Analysis Power-Aware Models Power-Aware Models System Level Verification Verification Design Power-Aware Power-Aware PCB Chip Design Design Package Test Test PCB Power-Aware Power-Aware PCB Design Power Integrity Power Integrity Place & Route Place & Route Multi-Corner Multi-Mode Multi-Corner Multi-Mode “Platform power is as important as core silicon power.” — Joe Macri, CTO, AMD Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 4 www.mentor.com
    • Low-Power Requirement vs. Power Trend Requirement Trend 3.5 3.0 2.5 Static Dynamic (W) 2.0 1.5 1.0 0.5 0.0 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 SOC Consumer Portable Power Trend Source: The International Technology Roadmap for Semiconductors (ITRS), 2008 Update Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 5 www.mentor.com
    • Low-Power Requirement vs. Power Trend Requirement 14.0 12.0 10.0 Static Dynamic 8.0 (W) 6.0 4.0 2.0 0.0 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 SOC Consumer Portable Power Trend Source: The International Technology Roadmap for Semiconductors (ITRS), 2009 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 6 www.mentor.com
    • Power Driven by Advanced Technology Adoption 250nm 130nm 90nm 65nm 45nm % of Total Silicon Demand Share 30% DVFS power gating multi-Vt 20% clock gating 10% 0% ’95 ’96 ’97 ’98 ’99 ’00 ’01 ’02 ’03 ’04 ’05 ’06 ’07 ’08 Source: VLSI Research, Silicon Demand, July 2008 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 7 www.mentor.com
    • Power Driven by Advanced Technology Adoption <=130nm 90nm 65nm 45 / 40nm % of TSMC Total Wafer Revenues 70% of Wafer Revenues 60% 40% 30% of Wafer Revenues 20% 16% of Wafer Revenues 9+% of Wafer Revenues 0% 7 6 9 8 1Q 4 5 9 ’0 ’0 ’0 ’0 ’0 ’0 ’0 1Q 4Q 1Q 3Q 1Q 1Q Source: TSMC Quarterly Reports Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 8 www.mentor.com
    • Power is *NOT* Scaling with Technology “In a decade, 11nm process technology could deliver devices with 16x more transistors running 2.4x faster than today's parts. But those devices will only use a 1/3 as much energy as today's parts, leaving engineers with a power budget so pinched they may be able to activate only 9% of those transistors.” –Mike Muller, CTO http://pc.watch.impress.co.jp/docs/2004/0524/epf01.jpg ARM http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=220900080 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 9 www.mentor.com
    • Lower Threshold: Higher Leakage Low Vt 90 nm Process High Vt 10000 1000 nW 100 10 1 0 16 32 48 64 80 96 12 28 44 60 76 92 08 24 40 56 72 88 04 20 36 52 68 84 00 16 32 48 64 80 96 12 28 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 Sorted Cell # “Managing leakage power at 90 nm and below” below” Barry Pangrle and Shekhar Kapoor , EEdesign.com, Nov 05, 2004 EEdesign.com, Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 10 www.mentor.com
    • Leakage vs. Delay Tradeoff 1000 90 nm Transistors 100 Ioff (nA/mm) 10 Ioffn 1 Ioffp 0.1 0.01 0.001 5 10 15 20 25 30 Gate Delay (pS) “Managing leakage power at 90 nm and below” , Pangrle and Kapoor , EEdesign.com, Nov 05, 2004 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 11 www.mentor.com
    • Leakage Exceeds Dynamic Power “DC power has exceeded AC power for the first time.” – John Y. Chen VP of Technology and Foundry Ops NVIDIA http://www.semiconductor.net/article/438968- http://www.scu.edu/engineering/ee/images/John_Chen_1.jpg Nvidia_s_Chen_Calls_for_Zero_Via_Defects.php Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 12 www.mentor.com
    • Body Bias has Diminishing Impact 0.15 G 130nm 0.1 210 mV S D 90nm ∆VTH (V) 0.05 95 mV B 0 55 mV 65nm -0.05 -0.1 -0.5 Reverse 0 Forward 0.5 VBS (V) “Low Power Design Essentials”, Jan Rabaey, 2009 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 13 www.mentor.com
    • When Power Doesn’t Scale … Power Density Clock Frequency 1000 Rocket Nozzle 100000 Inflection Point Inflection Point ~30GHz Nuclear Reactor 10000 100 P4D C2D P4 P4 C2DCi7 Watts/cm2 Pentium® III Ci7 Pentium® III 1000 Pentium® II P4D MHz MHz Hot Plate Pentium® II 10 Pentium® Pro Pentium® Pro 100 Pentium® Pentium® i486 i486 i386 i386 1 10 1µ 0.5µ 0.25µ 0.13µ 65nm ’87 ’92 ’97 ’02 ’07 ’10 “The numbers I would cite would be by 2010: 30GHz, 10billion transistors, and 1 tera-instruction per second.” --Pat Gelsinger, CTO, Intel April 9, 2002 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 14 www.mentor.com
    • Power Efficiency is the Main Goal “Achieving very high operating frequencies is no longer the prime target for new microprocessors. Instead, the goal has shifted to delivering higher performance combined with lower power. “Power efficiency” is the main scaling goal for chips used both in small hand held devices and in large data http://www.scu.edu/engineering/ee/images/John_Chen_1.jpg centers.” http://www.intel.com/pressroom/kits/bios/mbohr.htm –Mark T. Bohr, Intel Senior Fellow Intel http://blogs.intel.com/idf/2010/04/moores_law_after_32nm.php Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 15 www.mentor.com
    • Leading Processor Power Budgets I/O Mem I/O Clock Clock MPU1 Mem MPU2 Logic Logic I/O Clock Clock ASP1 ASP2 Logic Mem Mem Logic I/O • Power budgets of leading general purpose (MPU) and special purpose (ASP) processors Jan Rabaey, “Low Power Design Essentials”, various references Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 16 www.mentor.com
    • Clocks Power • Increases as skew and jitter decrease • Insertion delays increase, longer buffer chains, power increases clk Timing • Use skew to improve timing IR-Drop Power • Increases as skew decreases “0-skew” clk • Lower drop-> lower margin-> lower voltage-> less power • Reliability & noise Power • During test can cause good die to fail “∆-skew” clk ∆ ∆ Packaging • Ldi/dt, IR drop, thermal considerations Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 17 www.mentor.com
    • Low-Power Design and Multi-Core • Cores per die continues to increase April 2003 • Each core is a Single-Core 130nm April 2005 candidate for its own Dual-Core 90nm power island • As cores increase so do operating modes • Multi-Core chips are September 2007 June 2009 impractical w/o low- Quad-Core 65nm Hexa-Core 45nm power design Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 18 www.mentor.com
    • Low-Power Design Requires MCMM Cell Phone Chip Example Wally Rhines' DesignCon 2009 Keynote Address: “Common Wisdom Versus Reality in the More than 21 mode/corner scenarios Electronics Industry”, February 3, 2009 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 19 www.mentor.com
    • Concurrent Power and Timing Closure for Multi-Voltage Designs Core: Island1: 1.2v-1.8v Island1: 0.9v-1.5v 0.9v-1.5v ON/OFF ON/OFF Island2: Island2: 0.9v-1.5v 0.9v-1.5v 1.2v-1.8v 1.2v-1.8v Complexity Grows as More Domains are Added Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 20 www.mentor.com
    • EDA Waves • Tools and methodologies are always chasing the available capabilities of the existing technologies Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 21 www.mentor.com
    • The Next Big Wave • Increased design complexity due to the shear number of available gates demands higher- level tools Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 22 www.mentor.com
    • Why Optimize Power at the Architecture? Power Optimization Potential Architectural RTL Synthesis Gate Layout 0% 20% 40% 60% 80% 100% Source: LSI Logic Design and Optimization in the ESL Domain has the Biggest Impact on Power Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 23 www.mentor.com
    • Evolving Role of Design Phases in Overall System Power Minimization ESL (Behavioral) ESL (Behavioral) ESL 20% (Behavioral) ESL ESL 30% 40% (Behavioral) (Architectural) 50% ESL 20% (Architectural) RTL 10% 20% ESL RTL 10% (Architectural) ESL 30% (Architectural) 30% Physical 50% RTL 10% Physical 40% RTL 10% Physical 20% Physical 10% 2009 2011 2013 2015 Source: The International Technology Roadmap for Semiconductors (ITRS), 2009: Design Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 24 www.mentor.com
    • Low-Power Architectural Exploration “I want high-level tools to help me do design exploration.” Power Power tools for architecture exploration Rapid evaluation of the power and perf impact of architecture tradeoffs End-of-flow tools are not sufficient Low-power X Storage arrays, interconnect, etc… Custom design for power, not perf Optimized Vdd, Vt Bill Dally Bill Dally‘s 46th DAC Keynote Address: “The End of Denial Sr. VP Research, Nvidia Architecture and the Rise of Throughput Computing”, July 29, 2009 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 25 www.mentor.com
    • Architectural Impact on Low-Power Transmitter Min. Freq. to Area Average Design Achieve Req. Rate (mm2) Power (IFFT Block) (mW) 3.99 Comb ( 48 bfly4s ) 1.0 MHz 4.91 3.99 Piped ( 48 bfly4s ) 1.0 MHz 5.25 4.92 Folded ( 16 bfly4s ) 1.0 MHz 3.97 7.27 ~8.6x Folded ( 8 bfly4s ) 1.5 MHz 3.69 10.90 Folded ( 4 bfly4s ) 3.0 MHz 2.45 14.40 Folded ( 2 bfly4s ) 6.0 MHz 1.84 21.10 34.6 Folded ( 1 bfly4 ) 12.0 MHz 1.52 34.60 8.6x power variation resulted from architecture tradeoffs Source: “802.11a Transmitter: A case Study in Microarchitectural Exploration”, N. Dave et. al., Proceedings of MEMOCODE 2006 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 26 www.mentor.com
    • TSMC Sees the Importance of This Too ESL/HLS SiP ½ Node Design Challenges DFM AF Stat Tim’g DFM Pwr Mgmt Pwr CF SI CF Hier Flow Tim’g CF RF 5.0 RF 6.0 RF 7.0 RF 8.0 RF 9.0 RF 10.0 RF 11.0 2004 2005 2006 2007 2008 2009 2010 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 27 www.mentor.com
    • Example: Power Down / Up Sequence Power down sequence correctly executed for isolation, retention & power Corruption of internal nets during power down Output values restored at power up Outputs remain at Output values saved isolated value during retention during power down Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 28 www.mentor.com
    • Low-power Test Considerations Reduce Power During Test Test for Low-Power Designs Design partitioning Power information — Test in multiple sessions — UPF/P1801 — Untested cores use low power Test in presence of low- power features Low-power ATPG — DRC — Reduce switching during: — ATPG – Load – Capture Test of low-power features – Unload — Power gating control logic — Power metrics reporting — Retention cells — Constant flow compactor — Isolation cells — ATPG gater control — Level shifters 29 Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 29 www.mentor.com
    • Packaging Impacts Power • “These days about half of the dissipation in microprocessors comes from communication with external memory chips. If these chips are stacked together in 3D, communication energy cost might drop to a tenth.” – Bernard Meyerson, CTO of the Systems & Technology Group, IBM http://techon.nikkeibp.co.jp/article/HONSHI/20090527/170863/ Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 30 www.mentor.com
    • Power Issues Extend to the Board • ICs have a power problem Trends: – Lower & Multiple voltages/IC – Higher currents – Lower voltage supply tolerances • PCB power distribution networks are more complex – Multiple PDNs on single PCB – Requires “jigsaw” of split power / ground planes – Over-conservative design increases cost Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 31 www.mentor.com
    • Low-Power Flow Solution Design Verification TLM-Based TLM-Based RTL & Gates RTL & Gates ESL ESL Power-Aware IEEE Std 1801™-2009 Power-Aware IEEE Std 1801™-2009 Power-Aware Models Power-Aware Models HLS HLS Formal Checks Formal Checks Architectural Architectural Trade-Off Analysis Power Rule Checking Power Rule Checking Trade-Off Analysis Test Test Clock Crossings Clock Crossings Power-Aware Test Power-Aware Test Multiple Domain issues Multiple Domain Issues Issues issues Low-Power Test Low-Power Test Place & Route LVS // DRC LVS DRC Place & Route Layout-Level Layout-Level Multi-Corner Multi-Mode Multi-Corner Multi- Multi- Multi-Mode Power-Aware Checks Power-Aware Checks Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 32 www.mentor.com
    • Summary • Rescued by New Process Technology? – Not Likely Soon – Probably Will Get Worse Before it Gets Better • Standardized Formats – Significant Aid to Design & Verification Flows • Power is a System-Wide Optimization • Biggest Bang for the Buck is in Front-End Design Israel, May 4, 2010 © 2010 Mentor Graphics Corp. 33 www.mentor.com
    • Thank You! Israel, May 4, 2010 © 2010 Mentor Graphics Corp. www.mentor.com