Apache track d updated

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Apache track d updated

  1. 1. Comprehensive Low Power Design Analysis and Optimization An RTL to GDSII Approach Aveek Sarkar and Ronen Stilkol Apache Design Solutions
  2. 2. Power: The Metric For Chip Success <ul><li>Battery performance ~ f(operational and standby current) </li></ul><ul><li>Operational current </li></ul><ul><li>~ f(switching, short-circuit current) </li></ul><ul><li>~ f(logic, mode, frequency, library, PVT) </li></ul><ul><li>Standby current </li></ul><ul><li>~ f(sub-threshold/gate/junction leakage) </li></ul><ul><li>~ f(circuit, library, PVT) </li></ul><ul><li>Heat dissipation ~ f(current drawn, supply voltage) </li></ul>Power dissipated = voltage X current Current Drawn
  3. 3. Trends in Current Draw and Power Dissipation <ul><li>Both dynamic and standby (leakage currents) increasing with process </li></ul><ul><li>Need to control both </li></ul><ul><li>Supply voltage cannot scale sufficiently fast </li></ul><ul><li>Threshold voltage does not scale </li></ul>
  4. 4. Current and Voltage as Design Targets <ul><li>Circuit changes to “reduce” current increases voltage fluctuation </li></ul><ul><li>Reduced supply voltage + increased fluctuation affects NM </li></ul>1 1 Predict power accurately “early” 2 Predict power reduction possible 2 3 Identify achievable design changes 3 Power Number of RTL edits
  5. 5. Power in the RTL  GDS II Flow Target power reduction early in the design flow Ensure design verification to predict voltage drop noise from low power techniques Power reduction Usage Curve Power Integrity Usage Curve Physical Implementation & Signoff RTL Design & reduction Floor-planning & Synthesis Chip-Package-System Convergence
  6. 6. Techniques for Power Reduction An Analysis Driven Approach <ul><li>Early yet accurate analysis </li></ul><ul><ul><li>Before synthesis (logic) </li></ul></ul><ul><ul><li>Before routing (cap) </li></ul></ul><ul><li>Analysis driven reduction </li></ul><ul><ul><li>  Rapid, early identification of power hot-spots </li></ul></ul><ul><ul><li>  Power gating and voltage island prototyping </li></ul></ul><ul><ul><li>  Predictable power reduction: </li></ul></ul><ul><ul><li>clock, memory, datapath </li></ul></ul><ul><ul><li>  Power vs implementation overhead </li></ul></ul>
  7. 7. Operational Power Reduction Clock Tree Optimization RTL: Add and Improve Clock Enables Non-enabled Enabled sel sel_1d 1 R2 D RTL reductions make clock gating more effective EN CLK CG GCLK D EN CLK D Synthesis: Clock Gating RTL Gates
  8. 8. Operational Power Reduction Datapath Optimization
  9. 9. Standby Power Reduction Power Gating <ul><li>Advanced power gating modes give significant “standby” mode saving </li></ul><ul><li>Requires careful design and layout </li></ul>Power Gating Options Header Switches Footer Switches Block Vdd Vss CTL Block Vss Vdd CTL Dual Switches cntl1 cntl2 Ext VSS Int VSS Ext VDD Int VDD
  10. 10. <ul><li>Power gated domain transitions from off- to on-state </li></ul><ul><li>If in a driver-receiver pair, the receiver supply ramps up first, it causes high crowbar current scenario </li></ul>Power gating Clock gating Clock mode transitions generate transient event causing Ldi/dt noise Impact of Low Power Design Techniques on Power Integrity Constant activity Mode Clock gating mode
  11. 11. Impact of Design and Process Changes on Silicon Integrity
  12. 12. Low Power Design Verification Challenges <ul><li>Impact of package </li></ul><ul><li>Connection to die </li></ul><ul><li>Package routing and layers </li></ul><ul><li>Impact of decap </li></ul><ul><li>Decreasing efficiency </li></ul><ul><li>Leakage current trade-off </li></ul>Change in ESC/ESR for a decap cell Normalized against 130nm
  13. 13. Power Integrity Analysis for Low Power Designs <ul><li>DC (IR): </li></ul><ul><li>Static IR, power/signal EM </li></ul><ul><li>Transient (Ldi/dt + iR) </li></ul><ul><li>Functional mode </li></ul><ul><li>Test-mode (L/MBIST, scan) </li></ul><ul><li>Clock gating transition </li></ul><ul><li>Ramp-up and mixed-mode </li></ul>
  14. 14. Case Studies Bump Placement and Package Issues Highlighted <ul><li>High switching activity </li></ul><ul><li>Insufficient number of bumps </li></ul><ul><li>Incorrect package routing </li></ul><ul><li>Cluster of high power cells </li></ul><ul><li>Driving high load </li></ul><ul><li>Firing at same time </li></ul><ul><li>Insufficient package layers </li></ul><ul><li>Routing congestion </li></ul><ul><li>Fragmented routing ~ high L </li></ul>L di / dt ~ high DvD High drop area
  15. 15. Chip Package System Convergence An RTL to GDSII Focus 06/22/10 , RTL to GDS CPS Convergence RTL Design & reduction RTL Power Reduction RTL Power Analysis Floor-planning & Synthesis PG, IO Planning Early CPM Package/PCB planning Physical Implementation & Signoff IP Validation SoC Analysis Timing Impact CPS sign-off + cost down
  16. 16. <ul><li>Calhoun, B and Chandrakasan, A, “Static Noise Margin Variation for Sub-Threshold SRAM in 65-nm CMOS”, IEEE Journal of Solid State Circuits, vol 41, no 7, July 2006. </li></ul><ul><li>Cadence Design Systems, “A Practical Guide to Low-Power Design: User Experience with CPF”, Cadence Design Systems whitepaper , May 2008. </li></ul><ul><li>N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M. J. Irwin, M. Kandemir and V. Narayanan , “Leakage Current: Moore's Law Meets Static Power” , IEEE Transactions on Computers, Vol. 36, No. 12, December 2003, pp. 68-77. </li></ul><ul><li>L. K. Yong, F. Tan and C. S. Lee, “Power Noise Mitigation Strategy from RTL Perspective on MTCMOS Design”, DAC User Track presentation , DAC 2010, to appear. </li></ul><ul><li>A. Sarkar, “Power Noise Analysis for Next Generation ICs”, Apache Design Solutions whitepaper , June 2009. </li></ul>Selected References

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