Configurable FIFO• FIFO has two control signals: push and pop• Each time push is asserted, the designcaptures value present on in bus andstores it in internal memory.• Each time pop is asserted, the designdiscards the oldest value from internalmemory and drives the next (less old) valueon out bus.• Register Access Bus for FIFO ConfigurationFIFOpush popin outRegister Access
FIFO InterfaceName Bits Dir Descriptionclk 1 IN Clockrst 1 IN Active-high resetpush 1 IN Push data into a FIFOpop 1 IN Pop data out from FIFOempty 1 OUT FIFO is emptyfull 1 OUT FIFO is fullin Width IN FIFO Data Inout Width IN FIFO Data outcpu_req_data 8 IN Register Interface Inputcpu_rsp_data 8 OUT Register Interface Output
FIFO RegistersName Addr AccessTypeDescriptionMAX_DEPTH 0 RW Capacity of the FIFO. Valid range: from 2 to depth.Written value shall be less by one than the desiredcapacity. Recent written value is returned upon theread. Shall not be written while there are entries inthe FIFO.RPTR 1 R Current value of a read pointer is returned upon theread. Used for diagnostic purposes.WPTR 2 R Current value of a write pointer is returned upon theread. Used for diagnostic purposesTOTAL_ENTRIES 3 R Total number of values pushed into the FIFO sincethe recent reset. Used for statistic collection.
Register Interface• Packet-Based Interface:• Commands: IDLE, READ, WRITE, READ_REPLY,READ_ERROR, WRITE_ACK, WRITE_ERR• Address valid only for READ and WRITE;otherwise reserved• Value present only for READ_REPLY and WRITECommandValueAddress73 40
Property to Verify• For all possible configurations of FIFO_DEPTH,FIFO operation is valid.FIFOpush popin outRegister AccessProperty
FIFO Testbench• Re-used between Dynamic Simulation and FormalAnalysis with Panda FV• Parametric, with data width and FIFO depthFIFOpushpopin outRegister AccessDataDriverCheckerControlDriver
FIFO Formal Analysis• Run bounded model checking, 20-25 cyclesfrom initial state• Formal Analysis statically covers :– All possible configurations– All possible data increments– All possible push & pop timingsAs a result, thorough verification of configurableFIFO design