Configurable fifo with panda fv

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Formal Verrification of configurable FIFO design

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Configurable fifo with panda fv

  1. 1. Configurable FIFO with Panda FV
  2. 2. Configurable FIFO• FIFO has two control signals: push and pop• Each time push is asserted, the designcaptures value present on in bus andstores it in internal memory.• Each time pop is asserted, the designdiscards the oldest value from internalmemory and drives the next (less old) valueon out bus.• Register Access Bus for FIFO ConfigurationFIFOpush popin outRegister Access
  3. 3. FIFO InterfaceName Bits Dir Descriptionclk 1 IN Clockrst 1 IN Active-high resetpush 1 IN Push data into a FIFOpop 1 IN Pop data out from FIFOempty 1 OUT FIFO is emptyfull 1 OUT FIFO is fullin Width IN FIFO Data Inout Width IN FIFO Data outcpu_req_data 8 IN Register Interface Inputcpu_rsp_data 8 OUT Register Interface Output
  4. 4. FIFO RegistersName Addr AccessTypeDescriptionMAX_DEPTH 0 RW Capacity of the FIFO. Valid range: from 2 to depth.Written value shall be less by one than the desiredcapacity. Recent written value is returned upon theread. Shall not be written while there are entries inthe FIFO.RPTR 1 R Current value of a read pointer is returned upon theread. Used for diagnostic purposes.WPTR 2 R Current value of a write pointer is returned upon theread. Used for diagnostic purposesTOTAL_ENTRIES 3 R Total number of values pushed into the FIFO sincethe recent reset. Used for statistic collection.
  5. 5. Register Interface• Packet-Based Interface:• Commands: IDLE, READ, WRITE, READ_REPLY,READ_ERROR, WRITE_ACK, WRITE_ERR• Address valid only for READ and WRITE;otherwise reserved• Value present only for READ_REPLY and WRITECommandValueAddress73 40
  6. 6. Property to Verify• For all possible configurations of FIFO_DEPTH,FIFO operation is valid.FIFOpush popin outRegister AccessProperty
  7. 7. FIFO Testbench• Re-used between Dynamic Simulation and FormalAnalysis with Panda FV• Parametric, with data width and FIFO depthFIFOpushpopin outRegister AccessDataDriverCheckerControlDriver
  8. 8. Control Signals Generation
  9. 9. Register Interface• Goal: program FIFO depth randomly• Use parametric cell tbs_rnum to constantly generaterandom number from 2 to 16• Capture random data for register write access
  10. 10. Data Generation & CheckingGeneration:– Supply increasing numbers; choose randomincrement at the beginning of test:Data check:– Just check for data values increase with knownincrementGenerateradnom delta0 3 6 9 120 2 4 6 80 1 2 3 40 4 8 12 16…………
  11. 11. Data Generation Code
  12. 12. Data Checking CodeCheck if output data not increases with the givenincrement in the working mode (tcnt > 5):
  13. 13. FIFO Simulation
  14. 14. FIFO Formal Analysis• Run bounded model checking, 20-25 cyclesfrom initial state• Formal Analysis statically covers :– All possible configurations– All possible data increments– All possible push & pop timingsAs a result, thorough verification of configurableFIFO design

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