FPGA introduction for absolute beginners - What is inside FPGA (Altera example) - What are the major differences between firmware development for MCU and FPGA - Some very basics of Verilog HDL language (by similarities with C/C++) - Testbench approach and Icarus simulator demonstration - Altera Quartus IDE demonstration -- creating project, compilation, and download - Signal-Tap internal logic analyzer demonstration (Verilog source code examples attached inside presentation)

1. FPGA Workshop
Part 1: basics

2. Agenda
• What is FPGA and what inside FPGA
• What are the major differences between firmware development for
MCU and FPGA
• Some very basics of Verilog HDL language (by similarities with C/C++)
• Testbench approach and Icarus simulator demonstration
• Altera Quartus IDE demonstration -- creating project, compilation,
and download
• Signal-Tap internal logic analyzer demonstration

3. Situation on Embedded Market
From UBM Tech / EETimes Embedded Market 2015 survey

4. Situation on Embedded Market
From UBM Tech Embedded Market 2014 survey

5. Some history
• Creative logic designers realized
that small, fast PROMs could also
be configured to perform simple
logic functions.
• Semiconductor vendors began to
develop devices specifically
intended for logic applications. In
June 1975 Intersil Corp. introduced
the IM5200 PLA (Programmable
Logic Array).

6. Even in Russia (USSR)!
• Full reverse-engineered copy of Signetics's N82S101 PAL (December 1985)

7. From PROM to PAL

8. Macrocell / LE evolution

9. What is FPGA
• Ocean of interconnections, where islands are macrocells
(Cyclone IV GX)

10. Variety of Altera Cyclone family
Cyclone I Cyclone II Cyclone III
Cyclone III
LS
Cyclone IV
E
Cyclone IV
GX Cyclone V E
Cyclone V SE
(SoC)
Logic elements
2,910-
20,060
4,608-
68,416
5,136-
119,088
70,208-
198,464
6,272-
114,480
14,400-
149,760 25k-301k 25k-110k
Embedded Memory,
Kbits 59-288 117-1,125 414-3,888 2,997-8,019 270-3,888 540-6,480
1,760-
12,200 1,400-5,570
PLLs 1-2 2-4 2-4 4 2-4 3-8 4-8 5-9 (+3 in SoC)
Differential channels 34-129 58-262 70-233 113-181 66-230 25-216 112-240 74-144
18bit multipliers 23-288 200-396 15-266 0-360 50-684 72-224
Pins 100-400 144-896 144-780 484-780 144-780 169-896 383-896 484-896
Package TQFP, BGA TQFP, BGA EQFP, BGA BGA EQFP, BGA BGA BGA BGA
Additional functions
PCIe, 3.125 DDR
Gbps LVDS
DDR, Cortex-
A9 +
periphery
Core voltage 1.5V 1.2V 1.2V 1.2V 1V 1.2V 1.1V 1.1V
Price (digikey) $12-$124 $14-$353 $16-$483 $532-$1200 $11-$512 $25-$586 $34-$428 $60-$246
Process technology,
nm 130nm 90nm 65nm 65nm 60nm 28nm
Year introduced 2002 2004 2007 2007 2009 2011 ~2013

11. MCU vs FPGA from Hardware Engineer’s
perspective

12. How to program FPGA
• Draw logic circuit (using logic elements, flip-flops, counters, etc) – old
style, good control of results
• VHDL (first appeared 1980s) – developed by US Department of
Defense – has quite cumbersome syntax (imho)
• Verilog HDL (first appeared 1984) – developed by Cadence
• Using C/C++, Java, Python, etc libraries to describe and model digital
logic circuits – esoteric (not a state of the art)
• OpenCL – language for GPU programming, constrained by specific
hardware architecture

13. Anatomy of Hardware description languages
(HDL)

14. C vs Verilog
C/C++ Verilog
case sensitive case sensitive
{ … } begin … end (like in Pascal)
if (...) else if (...) else
type var; type var;
a = b; a = b;
==, <, > ==, <, >
&, |, ^ &, |, ^
+, -, *, / +, -, *, /
= (..) ? (..) : (..)= (..) ? (..) : (..) (ternary operator)
for (.., …, …) for (.., …, …)
while (…) while (…)
"bla-bla" "bla-bla"
// comment // comment

15. C vs Verilog
• C/C++ is for sequential computational model
• Verilog is for truly parallel computational model, i.e. your program is
executing completely in parallel unless you implement synchronization to
events
• Base unit in C – is a function, with input variables and return
• Base unit in Verilog – is a device, with input and output signals
(I.e. coding in Verilog and any other HDL requires changing a little bit
your way of thinking about program execution, you should think in
parallel way) => best analogs are interrupts or callback handlers in C

16. MCU firmware development cycle

17. FPGA firmware development cycle

18. The running light example

19. The running light example (cont.)

20. How to improve cycling shift?
Sequential assignments Parallel assignments
e
v
a
l
evaluation
Take subrange of vector
and concatenate
Parametrization by constant value
No more hodgie code!

21. Simple testbench (just for running our
module)

22. Simple testbench (just for running our
module) cont.

23. Icarus Verilog: freeware simulator
• Official site: http://iverilog.icarus.com/
• Download for Windows: http://bleyer.org/icarus/
• Online (not waveform viewer) http://www.iverilog.com/index.php

24. Simple .bat batch file: compile, run, view
Click for sources:

25. Altera Quartus II
Programmable logic device design software suite by Altera. The Web Edition is free, but only limited number of
FPGA families is supported. Updating every year (major version = year). Supported families set is changing also
for Web Edition every year (you should check supported families carefully before download).
Features:
• Analysis and synthesis of HDL designs (Verilog, VHDL, AHDL, circuit diagrams)
• RTL diagram viewer
• Timing analyzer, timing-driven synthesis
• ModelSim simulator (HDL pre-synthesis and post-fitting simulation)
• Qsys, a system-integration tool to generate FPGA-specific code pieces (PLLs, DRAM controllers, etc) or build
complete system with soft or hard processor core and peripherals
• SoC EDS, a set of development tools, utility programs, run-time software, and application examples to help
you develop software for SoC FPGA embedded systems.
• DSP Builder, a tool that creates a seamless bridge between the MATLAB/Simulink tool and Quartus II
software
• Firmware programming tool and SignalTap, the internal logic analyzer
(ps: we will use Quartus 11 because it supports Cyclone I)

26. FPGA logic compilation flow (in Quartus)

27. Quartus – starting new project
menu:
File >
New Project Wizard…
Next page #2:
add
RunningLight.v source file

28. Quartus – selecting FPGA chip
then press Finish

29. Project created!
Double click to open code
Top level entity code
Click to compile
Compilation messages

30. Logic compilation finished!

31. RTL Viewer
menu:
Tools >
Viewers >
RTL Viewer

32. Physical assignments: pins

33. Assigning pins
menu:
Assignments >
Pin Planner
Then compile!

34. Download firmware
menu:
Tools >
Programmer
Setup programming
hardware tool Specify what
you want
Will be download
directly to FPGA (not
in configuration
memory)

35. SignalTap II logic analyzer
• Full featured logic analyzer to see what inside FPGA
• One of the main debug tool
• Attaching to your design special part, no additional hardware needed
• Warning: it uses internal memory of FPGA and sometimes reducing
speed of your circuit

36. How to add SignalTap and signals to view
menu:
Tools >
SignalTap II
Logic analyzer
Setup programming
hardware tool
Specify recording
clock
Add signals
- Close, save and say
all Yes
- Recompile and
download to FPGA
again!

37. How to view
menu:
Tools >
SignalTap II
Logic analyzer
Press Run (one
shoot or
continuously)

38. Quartus Project (archived)
To open menu:
Project >
Restore Archived Project

39. Read more
• Verilog tutorial and reference: http://www.asic-
world.com/verilog/veritut.html
• Quartus tutorial: https://www.altera.com/content/dam/altera-
www/global/en_US/pdfs/literature/tt/tt_my_first_fpga.pdf
• Follow closely tutorial “DE0-Nano-SoC_My_First_FPGA.pdf“ for our
board: https://github.com/dwesterg/atlas-soc-
webcontent/blob/master/Documents/DE0-Nano-
SoC_My_First_FPGA.pdf