Pentium

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Pentium

  1. 1. Pentium Processor
  2. 2. 16-bit Processors and Segmentation (1978) <ul><ul><li>The IA-32 architecture family was preceded by 16-bit processors, the 8086 and 8088. </li></ul></ul><ul><ul><li>The 8086 has 16-bit registers and a 16-bit external data bus, with 20-bit addressing giving a 1-MByte address space. </li></ul></ul><ul><ul><li>The 8088 is similar to the 8086 except it has an 8-bit external data bus. The 8086/8088 introduced segmentation to the IA-32 architecture. </li></ul></ul><ul><ul><li>With segmentation, a 16-bit segment register contains a pointer to a memory segment of up to 64 KBytes. </li></ul></ul>
  3. 3. The Intel® 286 Processor (1982) <ul><li>The Intel 286 processor introduced protected mode operation into the IA-32 architecture. </li></ul><ul><li>Protected mode uses the segment register content as selectors or pointers into descriptor tables. </li></ul><ul><li>Descriptors provide 24-bit base addresses with a physical memory size of up to 16 Mbytes , support for virtual memory management on a segment swapping basis, and a number of protection mechanisms. These mechanisms include: </li></ul><ul><ul><ul><li>• Segment limit checking </li></ul></ul></ul><ul><ul><ul><li>• Read-only and execute-only segment options </li></ul></ul></ul><ul><ul><ul><li>• Four privilege levels </li></ul></ul></ul>
  4. 4. The Intel386™ Processor (1985) <ul><li>The Intel386 processor was the first 32-bit processor in the IA-32 architecture family. It introduced 32-bit registers for use both to hold operands and for addressing. </li></ul><ul><li>The lower half of each 32-bit Intel386 register retains the properties of the 16-bit registers of earlier generations, permitting backward compatibility. </li></ul><ul><li>The processor also provides a virtual-8086 mode that allows for even greater efficiency when executing programs created for </li></ul><ul><li>8086/8088 processors. </li></ul><ul><li>In addition, the Intel386 processor has support for: </li></ul><ul><ul><li>A 32-bit address bus that supports up to 4-GBytes of physical memory </li></ul></ul><ul><ul><li>A segmented-memory model and a flat memory model </li></ul></ul><ul><ul><li>Paging, with a fixed 4-KByte page size providing a method for virtual memory management </li></ul></ul><ul><ul><li>Support for parallel stages </li></ul></ul>
  5. 5. The Intel486™ Processor (1989) <ul><li>The Intel486™ processor added more parallel execution capability by expanding the Intel386 processor’s instruction decode and execution units into five pipelined stages. </li></ul><ul><li>Each stage operates in parallel with the others on up to five instructions in different stages of execution. </li></ul><ul><li>In addition, the processor added: </li></ul><ul><ul><li>An 8-KByte on-chip first-level cache that increased the percent of instructions that could execute at the scalar rate of one per clock. </li></ul></ul><ul><ul><li>An integrated x87 FPU </li></ul></ul><ul><ul><li>Power saving and system management capabilities </li></ul></ul>
  6. 6. The Intel® Pentium® Processor (1993) <ul><li>The introduction of the Intel Pentium processor added a second execution pipeline to achieve superscalar performance (two pipelines, known as u and v, together can execute two instructions per clock). </li></ul><ul><li>The on-chip first-level cache doubled, with 8 KBytes devoted to code and another 8 KBytes devoted to data. </li></ul><ul><li>The data cache uses the MESI protocol to </li></ul><ul><li>support more efficient write-back cache in addition to the write-through cache previously used by the Intel486 processor. </li></ul><ul><li>Branch prediction with an on-chip branch table was added to increase performance in looping constructs </li></ul>
  7. 7. PROCESSOR FEATURES OVERVIEW <ul><li>The Pentium processor supports the features of previous Intel Architecture processors and </li></ul><ul><li>provides significant enhancements including the following: </li></ul><ul><li>· Superscalar Architecture </li></ul><ul><li>· Dynamic Branch Prediction </li></ul><ul><li>· Pipelined Floating-Point Unit </li></ul><ul><li>· Improved Instruction Execution Time </li></ul><ul><li>· Separate Code and Data Caches. </li></ul><ul><li>· Writeback MESI Protocol in the Data Cache </li></ul><ul><li>· 64-Bit Data Bus </li></ul><ul><li>· Bus Cycle Pipelining </li></ul>
  8. 8. PROCESSOR FEATURES OVERVIEW <ul><li>Address Parity </li></ul><ul><li>· Internal Parity Checking </li></ul><ul><li>· Functional Redundancy Checking2 and Lock Step operation2 </li></ul><ul><li>· Execution Tracing </li></ul><ul><li>· Performance Monitoring </li></ul><ul><li>· IEEE 1149.1 Boundary Scan </li></ul>
  9. 9. PROCESSOR FEATURES OVERVIEW <ul><li>System Management Mode </li></ul><ul><li>Virtual Mode Extensions </li></ul><ul><li>Upgradable with a Pentium Over Drive processor2 </li></ul><ul><li>Dual processing support </li></ul><ul><li>Advanced SL Power Management Features </li></ul><ul><li>Fractional Bus Operation </li></ul><ul><li>On-Chip Local APIC Device </li></ul><ul><li>Functional Redundancy Checking and Lock Step operation </li></ul>
  10. 11. Pin Description
  11. 12. Pin Description
  12. 13. SUPER SCALAR <ul><li>A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate. </li></ul><ul><li>A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. </li></ul><ul><li>Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.. </li></ul>
  13. 14. Integer Instruction Pairing Rules <ul><li>The Pentium processor can issue one or two instructions every clock. In order to issue two instructions simultaneously they must satisfy the following conditions: </li></ul><ul><li>Both instructions in the pair must be “simple” as defined below Simple instructions are entirely hardwired; they do not require any microcode control and, in general, execute in one clock </li></ul><ul><li>There must be no read-after-write or write-after-write register dependencies between them. </li></ul><ul><li>Neither instruction may contain both a displacement and an immediate </li></ul><ul><li>Instructions with prefixes can only occur in the u-pipe. </li></ul><ul><li>Instruction prefixes are treated as separate 1-byte instructions. Sequencing hardware is used to allow them to function as simple instructions. </li></ul>
  14. 15. <ul><li>The following integer instructions are considered simple and may be paired: </li></ul><ul><li>1. mov reg, reg/mem/imm </li></ul><ul><li>2. mov mem, reg/imm </li></ul><ul><li>3. alu reg, reg/mem/imm </li></ul><ul><li>4. alu mem, reg/imm </li></ul><ul><li>5. inc reg/mem </li></ul><ul><li>6. dec reg/mem </li></ul><ul><li>7. push reg/mem </li></ul><ul><li>8. pop reg </li></ul><ul><li>9. lea reg,mem </li></ul><ul><li>10. jmp/call/jcc near </li></ul><ul><li>11. nop </li></ul><ul><li>12. test reg, reg/mem </li></ul><ul><li>13. test acc, imm </li></ul>

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