The  power  of partnership. The  triumph  of technology. VHDL Packages Coding Styles for Arithmetic Operations VHDL-200x A...
Agenda <ul><li>Introduction </li></ul><ul><li>VHDL Libraries & Packages </li></ul><ul><li>The Two Camps (IEEE vs Synopsys)...
Introduction <ul><li>VHDL is a strongly typed language </li></ul><ul><li>Allows overloading of operators/functions/procedu...
VHDL Libraries and Packages <ul><li>STD library packages </li></ul><ul><ul><li>standard, textio </li></ul></ul><ul><li>IEE...
STD.Standard <ul><li>VHDL Native Data Types </li></ul><ul><ul><li>boolean false, true </li></ul></ul><ul><ul><li>bit '0', ...
STD.Textio <ul><li>Constants </li></ul><ul><ul><li>input (STDIN), output (STDOUT) </li></ul></ul><ul><li>Data Types </li><...
IEEE.std_logic_1164 <ul><li>Data Types </li></ul><ul><ul><li>std_ulogic ('U','X','0','1','Z','W','L','H','-') </li></ul></...
IEEE.numeric_bit <ul><li>Data Types </li></ul><ul><ul><li>unsigned, signed --> array of bit </li></ul></ul><ul><li>Operato...
IEEE.numeric_std <ul><li>Data Types </li></ul><ul><ul><li>unsigned, signed --> array of std_logic </li></ul></ul><ul><li>O...
IEEE.math_real (not synthesizable*) <ul><li>Constants </li></ul><ul><ul><li>MATH_E, MATH_PI, ... </li></ul></ul><ul><li>Op...
IEEE.math_complex (not synthesizable) <ul><li>Data Types </li></ul><ul><ul><li>complex, complex_polar </li></ul></ul><ul><...
IEEE(synopsys).std_logic_arith <ul><li>Data Types </li></ul><ul><ul><li>signed, unsigned --> array of std_logic </li></ul>...
IEEE(synopsys).std_logic_signed <ul><li>Operators </li></ul><ul><ul><li>+, -, * </li></ul></ul><ul><ul><li><, <=, /=, =, =...
IEEE(synopsys).std_logic_unsigned <ul><li>Operators </li></ul><ul><ul><li>+, -, * </li></ul></ul><ul><ul><li><, <=, /=, =,...
IEEE(synopsys).std_logic_textio <ul><li>Procedures </li></ul><ul><ul><li>Read/Write ORead/OWrite, HRead/HWrite for std_(u)...
The two camps (IEEE vs Synopsys) <ul><li>IEEE version </li></ul><ul><ul><li>library IEEE; </li></ul></ul><ul><ul><li>use  ...
The two camps (cont.) <ul><li>Never mix the two libraries </li></ul><ul><ul><li>Either use numeric_std or std_logic_arith ...
The two camps (cont.) <ul><li>If you are using Synopsys version </li></ul><ul><ul><li>Never include both std_logic_unsigne...
Either Camp <ul><li>General recommendations </li></ul><ul><ul><li>Declare vectors as either signed or unsigned when approp...
Coding Arithmetic Operations in VHDL
Arithmetic Operations <ul><li>Note that /, rem and mod are only supported by numeric_std and not std_logic_arith! </li></ul>
Type Conversions/Resize
Additions/Subtraction <ul><li>General recommendations </li></ul><ul><ul><li>Always use signed/unsigned signals for its I/O...
Additions/Subtraction (cont.) <ul><li>Registered signed adder with carry </li></ul>signal a : signed(15 downto 0) signal b...
Multiplication <ul><li>General recommendations </li></ul><ul><ul><li>Always use signed/unsigned signals for its I/O </li><...
Multiplication (cont.) <ul><li>3-stage pipelined signed multiplier </li></ul>constant DEPTH : positive := 3; signal a  : s...
Divide (Remainder/Modulus) <ul><li>Different algorithms for divide </li></ul><ul><ul><li>Successive conditional subtract <...
Square Root <ul><li>Algorithms </li></ul><ul><ul><li>Restoring/non-restoring </li></ul></ul><ul><ul><li>CORDIC </li></ul><...
Trigonometric Functions <ul><li>Algorithms </li></ul><ul><ul><li>Lookup table based </li></ul></ul><ul><ul><li>CORDIC </li...
VHDL-200x Additions
http://www.eda.org/vhdl-200x/vhdl-200x-ft
STD.Standard (additions) <ul><li>Proposed additions to STD.Standard </li></ul><ul><ul><li>New Types </li></ul></ul><ul><ul...
STD.Textio (additions) <ul><li>Proposed additions to STD.Textio </li></ul><ul><ul><li>Functions and procedures </li></ul><...
IEEE.std_logic_1164 (additions) <ul><li>Proposed additions to IEEE.std_logic_1164 </li></ul><ul><ul><li>Operators </li></u...
IEEE.numeric_bit_unsigned (new) <ul><li>New unsigned functions/operators for bit_vector </li></ul><ul><ul><li>Arithmetic o...
IEEE.numeric_std (additions) <ul><li>Proposed additions to IEEE.numeric_std </li></ul><ul><ul><li>overloaded operators for...
IEEE.numeric_std_unsigned (new) <ul><li>New unsigned functions/operators for std_logic_vector </li></ul><ul><ul><li>Arithm...
IEEE.fixed_pkg (new) <ul><li>New fixed-point package </li></ul><ul><ul><ul><li>Various rounding, saturations styles </li><...
IEEE.float_pkg (new) <ul><li>New floating-point package </li></ul><ul><ul><ul><li>Various rounding styles, exponent, and f...
IEEE.float_alg_pkg (new) <ul><li>New floating-point algorithms package </li></ul><ul><ul><li>Complex add, subtract, multip...
Cores, cores, cores...
Reusable/Generic Code <ul><li>Design considerations </li></ul><ul><ul><li>Avoid using direct instantiation of primitive co...
Reusable/Generic Code (cont) <ul><li>Configuration </li></ul><ul><ul><li>Generic configurations (config_pkg) </li></ul></u...
Reusable/Generic Code (cont) <ul><li>Simple Arithmetic Operations (+, -, *) </li></ul><ul><ul><li>Write behavioral inferre...
Reusable/Generic Code (cont) <ul><li>Memories </li></ul><ul><ul><li>Create a wrapper for each memory </li></ul></ul><ul><u...
Conclusion
Conclusion <ul><li>Become familiar with VHDL standard packages and libraries </li></ul><ul><li>Use signed/unsigned for ari...
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VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions

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Describes the VHDL arithmetic packages and functions available. It also shows the new VHDL-200x packages and functions.

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VHDL Packages, Coding Styles for Arithmetic Operations and VHDL-200x Additions

  1. 1. The power of partnership. The triumph of technology. VHDL Packages Coding Styles for Arithmetic Operations VHDL-200x Additions
  2. 2. Agenda <ul><li>Introduction </li></ul><ul><li>VHDL Libraries & Packages </li></ul><ul><li>The Two Camps (IEEE vs Synopsys) </li></ul><ul><li>Coding Arithmetic Operations in VHDL </li></ul><ul><li>VHDL-200x Additions </li></ul><ul><li>Cores, cores, cores... </li></ul>
  3. 3. Introduction <ul><li>VHDL is a strongly typed language </li></ul><ul><li>Allows overloading of operators/functions/procedures. </li></ul><ul><li>Two different ways of coding arithmetic operations because of two different camps (IEEE, Synopsys) </li></ul><ul><li>IEEE is the recommended way, it is being revised by Accllera as new VHDL-200x </li></ul>
  4. 4. VHDL Libraries and Packages <ul><li>STD library packages </li></ul><ul><ul><li>standard, textio </li></ul></ul><ul><li>IEEE library packages +(new) </li></ul><ul><ul><li>std_logic_1164, numeric_bit, (numeric_bit_unsigned), numeric_std, (numeric_std_unsigned) math_real, math_complex, (fixed_generic_pkg), (fixed_pkg, float_generic_pkg), (float_pkg), (...) </li></ul></ul><ul><li>Synopsys library packages (compiled into IEEE library!) </li></ul><ul><ul><li>std_logic_arith, std_logic_unsigned, std_logic_signed, std_logic_misc, std_logic_textio </li></ul></ul>
  5. 5. STD.Standard <ul><li>VHDL Native Data Types </li></ul><ul><ul><li>boolean false, true </li></ul></ul><ul><ul><li>bit '0', '1' </li></ul></ul><ul><ul><li>character 256 ASCII </li></ul></ul><ul><ul><li>string array of character </li></ul></ul><ul><ul><li>integer -2 32-1 ... +(2 32-1 -1) </li></ul></ul><ul><ul><li>natural 0 ... +(2 32-1 -1) </li></ul></ul><ul><ul><li>positive 1 ... +(2 32-1 -1) </li></ul></ul><ul><ul><li>real -1.0E38 ... +1.0E38 </li></ul></ul><ul><ul><li>time 1 fs ... 1 hr </li></ul></ul>
  6. 6. STD.Textio <ul><li>Constants </li></ul><ul><ul><li>input (STDIN), output (STDOUT) </li></ul></ul><ul><li>Data Types </li></ul><ul><ul><li>LINE, TEXT, SIDE </li></ul></ul><ul><li>Procedures </li></ul><ul><ul><li>Read/Write for standard types </li></ul></ul><ul><ul><li>ReadLine/WriteLine </li></ul></ul>
  7. 7. IEEE.std_logic_1164 <ul><li>Data Types </li></ul><ul><ul><li>std_ulogic ('U','X','0','1','Z','W','L','H','-') </li></ul></ul><ul><ul><li>std_logic resolved of std_ulogic </li></ul></ul><ul><ul><li>std_ulogic_vector array of std_ulogic </li></ul></ul><ul><ul><li>std_logic_vector array of std_logic </li></ul></ul><ul><li>Operators </li></ul><ul><ul><li>Boolean (and/or/nand/nor/xor/xnor/not) </li></ul></ul><ul><li>Functions </li></ul><ul><ul><li>Conversion From/To std_(u)logic(_vector) To/From bit(_vector), to_x01, is_x </li></ul></ul><ul><ul><li>rising_edge/falling_edge for std_(u)logic </li></ul></ul>
  8. 8. IEEE.numeric_bit <ul><li>Data Types </li></ul><ul><ul><li>unsigned, signed --> array of bit </li></ul></ul><ul><li>Operators </li></ul><ul><ul><li>Arithmetic: +, -, *, /, rem, mod </li></ul></ul><ul><ul><li>Relational: <, <=, =, /=, =>, > </li></ul></ul><ul><ul><li>Shift/Rotate: sll, srl, rol, ror </li></ul></ul><ul><ul><li>Bitwise: and, nand, or, nor, xor, xnor, not </li></ul></ul><ul><li>Functions </li></ul><ul><ul><li>abs, shift_left, shift_right, rotate_left, rotate_right </li></ul></ul><ul><ul><li>resize, to_integer, to_signed, to_unsigned </li></ul></ul><ul><ul><li>rising_edge, falling_edge for bit (will move to STD.standard) </li></ul></ul>
  9. 9. IEEE.numeric_std <ul><li>Data Types </li></ul><ul><ul><li>unsigned, signed --> array of std_logic </li></ul></ul><ul><li>Operators </li></ul><ul><ul><li>Arithmetic: +, -, *, /, rem, mod </li></ul></ul><ul><ul><li>Relational: <, <=, =, /=, =>, > </li></ul></ul><ul><ul><li>Shift/Rotate: sll, srl, rol, ror </li></ul></ul><ul><ul><li>Bitwise: and, nand, or, nor, xor, xnor, not </li></ul></ul><ul><li>Functions </li></ul><ul><ul><li>abs, shift_left, shift_right, rotate_left, rotate_right </li></ul></ul><ul><ul><li>resize, to_integer, to_signed, to_unsigned </li></ul></ul><ul><ul><li>std_match, to_01 </li></ul></ul>
  10. 10. IEEE.math_real (not synthesizable*) <ul><li>Constants </li></ul><ul><ul><li>MATH_E, MATH_PI, ... </li></ul></ul><ul><li>Operators for real </li></ul><ul><ul><li>mod, **, </li></ul></ul><ul><li>Functions accepting real returning real </li></ul><ul><ul><li>sign, ceil, floor, round, trunc, realmax, realmin, sqrt, cbrt, exp, log, log2*, log10 </li></ul></ul><ul><ul><li>sin, cos, tan, arcsin, arccos, arctan </li></ul></ul><ul><ul><li>sinh, cosh, tanh, arcsinh, arccosh, arctanh </li></ul></ul><ul><li>Procedures </li></ul><ul><ul><li>uniform: Pseudo-random number (0.0, 1.0) </li></ul></ul>
  11. 11. IEEE.math_complex (not synthesizable) <ul><li>Data Types </li></ul><ul><ul><li>complex, complex_polar </li></ul></ul><ul><ul><li>positive_real, principal_value (-  .. +) </li></ul></ul><ul><li>Operators </li></ul><ul><ul><li>+, -, *, /, =, /= </li></ul></ul><ul><li>Functions </li></ul><ul><ul><li>complex_to_polar, polar_to_complex </li></ul></ul><ul><ul><li>abs, arg, conj, sqrt, exp, log, log2, log10 </li></ul></ul><ul><ul><li>sin, cos, tan, arcsin, arccos, arctan </li></ul></ul><ul><ul><li>sinh, cosh, tanh, arcsinh, arccosh, arctanh </li></ul></ul>
  12. 12. IEEE(synopsys).std_logic_arith <ul><li>Data Types </li></ul><ul><ul><li>signed, unsigned --> array of std_logic </li></ul></ul><ul><ul><li>small_int --> 0, 1 </li></ul></ul><ul><li>Operators </li></ul><ul><ul><li>Arithmetic: +, -, * </li></ul></ul><ul><ul><li>Relational: <, <=, =, /=, =>, > </li></ul></ul><ul><ul><li>Shift: shr, shl </li></ul></ul><ul><li>Functions </li></ul><ul><ul><li>conv_integer, conv_signed, conv_unsigned, conv_std_logic_vector </li></ul></ul><ul><ul><li>ext, sxt </li></ul></ul>
  13. 13. IEEE(synopsys).std_logic_signed <ul><li>Operators </li></ul><ul><ul><li>+, -, * </li></ul></ul><ul><ul><li><, <=, /=, =, =>, > </li></ul></ul><ul><li>Functions </li></ul><ul><ul><li>abs </li></ul></ul><ul><ul><li>shl, shr </li></ul></ul><ul><ul><li>conv_integer </li></ul></ul>
  14. 14. IEEE(synopsys).std_logic_unsigned <ul><li>Operators </li></ul><ul><ul><li>+, -, * </li></ul></ul><ul><ul><li><, <=, /=, =, =>, > </li></ul></ul><ul><li>Functions </li></ul><ul><ul><li>shl, shr </li></ul></ul><ul><ul><li>conv_integer </li></ul></ul>
  15. 15. IEEE(synopsys).std_logic_textio <ul><li>Procedures </li></ul><ul><ul><li>Read/Write ORead/OWrite, HRead/HWrite for std_(u)logic(_vector) </li></ul></ul><ul><li>Contents will be moved to std_logic_1164 for VHDL-200x </li></ul>
  16. 16. The two camps (IEEE vs Synopsys) <ul><li>IEEE version </li></ul><ul><ul><li>library IEEE; </li></ul></ul><ul><ul><li>use IEEE.std_logic_1164.all; </li></ul></ul><ul><ul><li>use IEEE. numeric_bit.all; or numeric_std.all; </li></ul></ul><ul><li>Synopsys version </li></ul><ul><ul><li>library IEEE; </li></ul></ul><ul><ul><li>use IEEE.std_logic_1164.all; </li></ul></ul><ul><ul><li>use IEEE.std_logic_arith.all; </li></ul></ul><ul><ul><li>use IEEE.std_logic_unsigned.all; </li></ul></ul><ul><ul><li>use IEEE.std_logic_signed.all; </li></ul></ul>
  17. 17. The two camps (cont.) <ul><li>Never mix the two libraries </li></ul><ul><ul><li>Either use numeric_std or std_logic_arith but not both </li></ul></ul><ul><ul><li>numeric_std and std_logic_unsigned could be used together until VHDL-200x is complete. There will be new packages numeric_bit_unsigned and numeric_std_unsigned. </li></ul></ul><ul><ul><li>For standard compatibility and for compliance with the future VHDL-200x, it is recommended to become familiar with numeric_bit, numeric_std and maybe use them in new designs. </li></ul></ul>
  18. 18. The two camps (cont.) <ul><li>If you are using Synopsys version </li></ul><ul><ul><li>Never include both std_logic_unsigned and std_logic_signed together. This will create too many ambiguities for the compiler. </li></ul></ul><ul><ul><li>It is best to include std_logic_arith only and declare variables as signed or unsigned explicitly and not rely on the implicit conversions </li></ul></ul>
  19. 19. Either Camp <ul><li>General recommendations </li></ul><ul><ul><li>Declare vectors as either signed or unsigned when appropriate. </li></ul></ul><ul><ul><ul><li>The port/signal shows the intention of the designer </li></ul></ul></ul><ul><ul><ul><li>Easier arithmetic operations and no ambiguity in synthesis/simulation </li></ul></ul></ul><ul><ul><ul><li>This should be done even at the I/O ports (except at the top-level) </li></ul></ul></ul><ul><ul><li>For counters, try using constrained integer </li></ul></ul><ul><ul><ul><li>e.x.: signal counter : integer range 0 to 255; </li></ul></ul></ul><ul><ul><ul><li>Performance (24-bit counter) </li></ul></ul></ul>integer bit_vector std_logic_vector 22 s 713 ms 31 s 369 ms 32 s 756 ms
  20. 20. Coding Arithmetic Operations in VHDL
  21. 21. Arithmetic Operations <ul><li>Note that /, rem and mod are only supported by numeric_std and not std_logic_arith! </li></ul>
  22. 22. Type Conversions/Resize
  23. 23. Additions/Subtraction <ul><li>General recommendations </li></ul><ul><ul><li>Always use signed/unsigned signals for its I/O </li></ul></ul><ul><ul><li>Result could be one bit wider </li></ul></ul><ul><ul><ul><li>Sign extend the input if you want the full resolution </li></ul></ul></ul><ul><ul><ul><li>Otherwise, carry/borrow will be lost </li></ul></ul></ul><ul><ul><li>Always register the output </li></ul></ul><ul><ul><li>More pipeline registers could be added if wider adder/subtracter is used </li></ul></ul><ul><li>Synthesis tools infer and choose the best implementation (ripple carry, CLA, CSA, ..) based on timing/area constraints </li></ul>
  24. 24. Additions/Subtraction (cont.) <ul><li>Registered signed adder with carry </li></ul>signal a : signed(15 downto 0) signal b : signed(15 downto 0) signal c : signed(16 downto 0) p_Add_With_Carry: process( clock ) begin if rising_edge(clock) then c <= resize(a, c'length) + resize(b, c'length); end if; end process p_Add_With_Carry; signal a : signed(15 downto 0) signal b : signed(15 downto 0) signal c : signed(16 downto 0) p_Add_With_Carry: process( clock ) begin if rising_edge(clock) then c <= conv_signed(a, c'length) + conv_signed(b, c'length); end if; end process p_Add_With_Carry; numeric_std std_logic_arith c a b
  25. 25. Multiplication <ul><li>General recommendations </li></ul><ul><ul><li>Always use signed/unsigned signals for its I/O </li></ul></ul><ul><ul><li>Result width is the sum of the input widths </li></ul></ul><ul><ul><li>Most multipliers need to be pipelined </li></ul></ul><ul><ul><li>Synthesis tools infer and choose the best implementation (Booth, Wallace tree, ...) based on timing/area constraints </li></ul></ul>
  26. 26. Multiplication (cont.) <ul><li>3-stage pipelined signed multiplier </li></ul>constant DEPTH : positive := 3; signal a : signed(15 downto 0) signal b : signed(10 downto 0) signal c : signed(a'length+b'length-1 downto 0); type Pipe_Type is array(0 to DEPTH-1) of signed(c'range); signal pipe : Pipe_Type; p_Mult_pipe: process( clock ) begin if rising_edge(clock) then pipe <= signed(a * b) & pipe(0 to pipe'length-2); end if; end process p_Mult_pipe; c <= pipe(pipe'length-1); c a b
  27. 27. Divide (Remainder/Modulus) <ul><li>Different algorithms for divide </li></ul><ul><ul><li>Successive conditional subtract </li></ul></ul><ul><ul><ul><li>Restoring/non-restoring </li></ul></ul></ul><ul><ul><li>Fast dividers (carry-propagation free add/sub) </li></ul></ul><ul><ul><ul><li>SRT (different radix sizes) </li></ul></ul></ul><ul><li>Most can be pipelined </li></ul><ul><li>Most synthesis tools do not support divider inference </li></ul>
  28. 28. Square Root <ul><li>Algorithms </li></ul><ul><ul><li>Restoring/non-restoring </li></ul></ul><ul><ul><li>CORDIC </li></ul></ul><ul><ul><li>... </li></ul></ul>
  29. 29. Trigonometric Functions <ul><li>Algorithms </li></ul><ul><ul><li>Lookup table based </li></ul></ul><ul><ul><li>CORDIC </li></ul></ul><ul><ul><li>... </li></ul></ul>
  30. 30. VHDL-200x Additions
  31. 31. http://www.eda.org/vhdl-200x/vhdl-200x-ft
  32. 32. STD.Standard (additions) <ul><li>Proposed additions to STD.Standard </li></ul><ul><ul><li>New Types </li></ul></ul><ul><ul><ul><li>boolean_vector, integer_vector, real_vector, time_vector </li></ul></ul></ul><ul><ul><li>New Operators </li></ul></ul><ul><ul><ul><li>“??” bit to boolean </li></ul></ul></ul><ul><ul><ul><ul><li>ex.: (a <= ??b;) = (if b='1' {a<=true} else {a<=false}) </li></ul></ul></ul></ul><ul><ul><ul><li>“?=” “?/=” “?>” “?>=” “?<” “?<=” shorthand if/else bit/bool </li></ul></ul></ul><ul><ul><ul><ul><li>e.x.: (a <= b ?= c;) = (if b=c { a<='1' } a<='0'; }) </li></ul></ul></ul></ul><ul><ul><li>New Functions </li></ul></ul><ul><ul><ul><li>Boolean reduction (and_reduce, nand_reduce, ...) </li></ul></ul></ul><ul><ul><ul><li>Boolean array + scalar operators (and, nand, ...) </li></ul></ul></ul><ul><ul><ul><li>minimum/maximum for primitive types </li></ul></ul></ul><ul><ul><ul><li>rising_edge, falling_edge for type bit </li></ul></ul></ul>
  33. 33. STD.Textio (additions) <ul><li>Proposed additions to STD.Textio </li></ul><ul><ul><li>Functions and procedures </li></ul></ul><ul><ul><ul><li>Read/Write to/from string </li></ul></ul></ul><ul><ul><ul><ul><li>sread/swrite </li></ul></ul></ul></ul><ul><ul><ul><li>Binray/Octal/Hex Read/Write </li></ul></ul></ul><ul><ul><ul><ul><li>bread/bwrite, oread/owrite, hread, hwrite </li></ul></ul></ul></ul><ul><ul><ul><li>Read/Write for new vector types </li></ul></ul></ul><ul><ul><ul><ul><li>boolean_vector, integer_vector, real_vector, time_vector </li></ul></ul></ul></ul><ul><ul><ul><li>String justify and to_string, to_ostring, to_hstring for basic types </li></ul></ul></ul>
  34. 34. IEEE.std_logic_1164 (additions) <ul><li>Proposed additions to IEEE.std_logic_1164 </li></ul><ul><ul><li>Operators </li></ul></ul><ul><ul><ul><li>“??” std_logic to boolean </li></ul></ul></ul><ul><ul><ul><li>“?=” “?/=” “?>” “?>=” “?<” “?<=” shorthand if/else std_logic/std_logic_vector to boolean </li></ul></ul></ul><ul><ul><li>Functions and procedures </li></ul></ul><ul><ul><ul><li>to_bit_vector, to_std_logic_vector </li></ul></ul></ul><ul><ul><ul><li>Shift and rotate for std_logic_vector (sll, srl, rol, ror) </li></ul></ul></ul><ul><ul><ul><li>Vector-scalar bitwise operations (and, or, ...) </li></ul></ul></ul><ul><ul><ul><li>Boolean bitwise std_logic -> std_logic </li></ul></ul></ul><ul><ul><ul><li>Reduction functions for std_logic_vector (or_reduce, ...) </li></ul></ul></ul><ul><ul><ul><li>Read/Write (decimal, binary, octal, hex) for std_logic_vector </li></ul></ul></ul><ul><ul><ul><li>to_string, to_bstring, to_ostring, to_hstring </li></ul></ul></ul>
  35. 35. IEEE.numeric_bit_unsigned (new) <ul><li>New unsigned functions/operators for bit_vector </li></ul><ul><ul><li>Arithmetic operators </li></ul></ul><ul><ul><ul><li>+, -, *, /, mod, rem </li></ul></ul></ul><ul><ul><li>Logical operators </li></ul></ul><ul><ul><ul><li><, <=, =, /=, =>, > </li></ul></ul></ul><ul><ul><li>Shift, rotate and resize for bit_vector (unsigned) </li></ul></ul><ul><ul><li>Maximum, minimum </li></ul></ul><ul><ul><li>find_lsb, find_lsb </li></ul></ul><ul><ul><li>Shorthand compare to boolean (?=, ?/=, ...) </li></ul></ul>
  36. 36. IEEE.numeric_std (additions) <ul><li>Proposed additions to IEEE.numeric_std </li></ul><ul><ul><li>overloaded operators for std_logic and signed/unsigned </li></ul></ul><ul><ul><ul><li>+, -, bitwise (and, or, ..) </li></ul></ul></ul><ul><ul><li>New overloads for resize, to_unsigned, and to_signed with a vector as new size </li></ul></ul><ul><ul><li>New overloads for signed/unsigned input </li></ul></ul><ul><ul><ul><li>Shorthand conditional operators (?=, ?/=, ...) </li></ul></ul></ul><ul><ul><ul><li>Shift operators (sla, sra) </li></ul></ul></ul><ul><ul><ul><li>Functions: maximum, minimum, find_lsb, find_msb </li></ul></ul></ul><ul><ul><ul><li>Reductions (and_reduce, ...) </li></ul></ul></ul><ul><ul><ul><li>add_sign, remove_sign, various to_strings, various read/write </li></ul></ul></ul>
  37. 37. IEEE.numeric_std_unsigned (new) <ul><li>New unsigned functions/operators for std_logic_vector </li></ul><ul><ul><li>Arithmetic operators </li></ul></ul><ul><ul><ul><li>+, -, *, /, mod, rem </li></ul></ul></ul><ul><ul><li>Logical operators </li></ul></ul><ul><ul><ul><li><, <=, =, /=, =>, > </li></ul></ul></ul><ul><ul><li>Shift, rotate and resize for std_logic_vector (unsigned) </li></ul></ul><ul><ul><li>Maximum, minimum </li></ul></ul><ul><ul><li>find_lsb, find_lsb </li></ul></ul><ul><ul><li>Shorthand compare to boolean (?=, ?/=, ...) </li></ul></ul>
  38. 38. IEEE.fixed_pkg (new) <ul><li>New fixed-point package </li></ul><ul><ul><ul><li>Various rounding, saturations styles </li></ul></ul></ul><ul><ul><ul><ul><li>Implemented as constant, but will use package generics when new VHDL-200x is finalized </li></ul></ul></ul></ul><ul><ul><ul><li>New Data Types </li></ul></ul></ul><ul><ul><ul><ul><li>Unsigned/Signed fixed-point (ufixed, sfixed) </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Decimal point between index 0 and -1 </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>e.x.: sfixed(1, -2) { “xx.xx” -> range [-2.0 .. +1.75] } </li></ul></ul></ul></ul></ul><ul><ul><ul><li>Operators/Functions (overloads for real/integer and sfixed/ufixed) </li></ul></ul></ul><ul><ul><ul><ul><li>Abs, +, -, *, /, mod, rem </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Divide, reciprocal, remainder, modulo, scalb </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Logical (<, <=, ...) and shorthand logical (?=, ?/=, ...) </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Shift/rotate, bitwise, reduction, resize, conversion and to_string, from_string, and various read/write </li></ul></ul></ul></ul>
  39. 39. IEEE.float_pkg (new) <ul><li>New floating-point package </li></ul><ul><ul><ul><li>Various rounding styles, exponent, and fraction widths </li></ul></ul></ul><ul><ul><ul><ul><li>Implemented as constant, but will use package generics when new VHDL-200x is finalized </li></ul></ul></ul></ul><ul><ul><ul><li>New Data Types </li></ul></ul></ul><ul><ul><ul><ul><li>Generic (float), IEEE-754 single precision (float32), IEEE-754 double precision (float64), Long Double (float128) </li></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Array of std_logic </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>e.x.: float32 = float(8, -23) {sign+8 exp+24 fract} </li></ul></ul></ul></ul></ul><ul><ul><ul><li>Operators/Functions (overloads for real/integer and sfixed/ufixed) </li></ul></ul></ul><ul><ul><ul><ul><li>+, -, *, /, mod, rem </li></ul></ul></ul></ul><ul><ul><ul><ul><li>Add, subtract, multiply, divide, remainder, modulo, reciprocal, dividebyp2, mac, eq, ne, lt, gt, le, ge, conversion and to_string, from_string, and various read/write </li></ul></ul></ul></ul>
  40. 40. IEEE.float_alg_pkg (new) <ul><li>New floating-point algorithms package </li></ul><ul><ul><li>Complex add, subtract, multiply, divide, to polar, from polar, sqrt </li></ul></ul><ul><ul><li>Floating point nr_divide, nr_reciprocal, sqrt, cbrt, inverse_sqrt, exp, log, power_of, ln, **, sin, cos, tan, arcsin, arccos, arctan </li></ul></ul>
  41. 41. Cores, cores, cores...
  42. 42. Reusable/Generic Code <ul><li>Design considerations </li></ul><ul><ul><li>Avoid using direct instantiation of primitive components unless at the top, I/O level </li></ul></ul><ul><ul><li>It is best to put technology dependent instantiations in one file (I/O is recommended) </li></ul></ul><ul><li>Main concerns </li></ul><ul><ul><li>Arithmetic operations </li></ul></ul><ul><ul><li>Memories </li></ul></ul><ul><ul><li>Other cores </li></ul></ul>
  43. 43. Reusable/Generic Code (cont) <ul><li>Configuration </li></ul><ul><ul><li>Generic configurations (config_pkg) </li></ul></ul><ul><ul><ul><li>Constants and types for different technologies/chips </li></ul></ul></ul><ul><ul><li>Chips specific configuration (config_hill_pkg) </li></ul></ul><ul><ul><ul><li>Constants for configuring a specific chip </li></ul></ul></ul>Package config_pkg is type TARGET_TYPE is (FPGA, ASIC); type VENDOR_TYPE is (XILINX, IBM, LSI, ...); type XILINX_PARTS is (Virtex2, Virtex4, ...); type IBM_PROCESSES is (G4, G5, ...); type LSI_PROCESSES is (Flex, Gflex, ...); End Package config_pkg; Package hill_config_pkg is -- Chip specific parameters constant DEVICE_ID : ... = ...; constant HAS_CLOCK_ERROR : boolean := TRUE; constant VITERBI_TRACE_BACK : positive := ...; constant HAS_FLASH : boolean := TRUE; constant FLASH_DATA_SIZE : positive := 16; End Package hill_config_pkg;
  44. 44. Reusable/Generic Code (cont) <ul><li>Simple Arithmetic Operations (+, -, *) </li></ul><ul><ul><li>Write behavioral inferred code (signed/unsigned) </li></ul></ul><ul><ul><ul><li>Note: / and rem could be coded in RTL </li></ul></ul></ul><ul><li>Complex arithmetic or cores (/, mod, rem, sqrt, ...) </li></ul><ul><ul><li>Write a wrapper and instantiate the appropriate technology dependent component </li></ul></ul>a <= b * c; d <= a + d; g_XILINX_V2: if ( TARGET=XILINX_V2 ) generate u_div: generic_divider generic map (...) port map (...); end generate; g_IBM_G5: if ( TARGET=IBM_G5 ) generate u_div: DW_DIV port map (....); end generate;
  45. 45. Reusable/Generic Code (cont) <ul><li>Memories </li></ul><ul><ul><li>Create a wrapper for each memory </li></ul></ul><ul><ul><li>Instantiate technology dependent memory based on a generic passed to the wrapper </li></ul></ul>Entity memory is generic (TARGET : TARGET_TYPE ); ... begin g_Xilinx_V2: if ( TARGET=X_V2 ) generate u_mem : block_memory_RW generic map (...) port map (...); end generate; g_LSI_GFlex: if ( TARGET=LSI_GFlex ) generate u_mem : m1r2d_xyz port map (...); end generate; End Entity memory;
  46. 46. Conclusion
  47. 47. Conclusion <ul><li>Become familiar with VHDL standard packages and libraries </li></ul><ul><li>Use signed/unsigned for arithmetic operations </li></ul><ul><li>Write generic technology independent code </li></ul><ul><li>Use wrapper for memories, technology dependent cores </li></ul>

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