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EFFICIENT VLSI IMPLEMENTATION OF THE BLOCK CIPHER RIJNDAEL ALGORITHM
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EFFICIENT VLSI IMPLEMENTATION OF THE BLOCK CIPHER RIJNDAEL ALGORITHM

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RIJNDAEL ALGORITHM …

RIJNDAEL ALGORITHM
SYSTEM ARCHITECTURE
SIMULATION RESULTS
FUTURE DEVELOPMENT

Published in: Design

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  • 1. EFFICIENT VLSI IMPLEMENTATION OF THE BLOCK CIPHER RIJNDAEL ALGORITHM R.V.S COLLEGE OF ENGINEERING & TECHNOLOGY DINDIGUL AJAL.A.J & VELMURUGAN.S DEPT OF ECE
  • 2. PRESENTATION OVERVIEW • INTRODUCTION • RIJNDAEL ALGORITHM • SYSTEM ARCHITECTURE • SIMULATION RESULTS • FUTURE DEVELOPMENT • CONCLUSION
  • 3. INTRODUCTION • The cipher Rijndael is one of the five finalists of the Advanced Encryption Standard (AES) • The algorithm has been designed by Joan Daemen and Vincent Rijmen • It is a Block cipher. • The hardware implementation with 128-bit blocks and 128-bit keys is presented. • VLSI optimizations of the Rijndael algorithm are discussed and several hardware design modifications and techniques are used, such as memory sharing and parallelism.
  • 4. Critical communications private(confidentiality) Know who we are dealing with (identity) Guarantee messages unaltered (integrity) Assert rights over content use (authorization) All critical systems up-and- running(availability) Critical N/W Security Elements
  • 5. The Rijndael Chip AES 128bit implementation The Rijndael chip Selected by AES (Advanced Encryption Standard, part of NIST) as the new private-key encryption standard.
  • 6. Add Round Key Sub Bytes Shift Rows Mix Columns Add Round Key Sub Bytes Shift Rows Mix Columns Add Round Key Sub Bytes Shift Rows Add Round Key Add Round Key Inv Sub Bytes Inv Shift Rows Inv Mix Columns Add Round Key Inv Sub Bytes Inv Shift Rows Inv Mix Columns Add Round Key Inv Sub Bytes Inv Shift Rows Add Round Key 1 9 10 1 2 10 9 Encryption Decryption Partition of the rounds not suited for intraround pipelining Rijndael Algorithm – Round
  • 7. Rijndael Architecture - Overview Parallel Round 1 Round Key Register Parallel Round 2 Key Generator AddKey DataRegKeyReg Controller 128 12832 32 32128 128 128 128 128 DataReg Largest potential for optimizations in rounds
  • 8. It all starts with a key • What is a key? • Encryption algorithm is like a recipe for spaghetti. Key is like the choice of sauce that changes the end result. Encrypt – Garble so it’s unreadable Decrypt – Ungarble so it can be read again Plain text I am going to the market encrypt algorithm – add x letters key - 2 hard to read, UNLESS you know the key Cipher text K co iqkpi vq vjg octmgv Encrypting Text Plain text I am going to the market CipherText K co iqkpi vq vjg octmgv decryption algorithm – subtract x letters key - 2 Decrypting Text That’s encryption!
  • 9. BLOCK DIAGRAM - DECRYPTION CORES
  • 10. Encryption Path Decryption Path SubBytes Inv Sub Bytes InvAffTrans MultInverse AffTrans Rijndael S-box consists of two operations Parallel impletation of S-Boxes Multiplicative inverse can be shared MultInverse
  • 11. HDL SYNTHESIS REPORT Macro Statistics # ROMs : 56 16x128-bit ROM : 56 # Multiplexers : 66 8-bit 10-to-1 MUX : 10 8-bit 16-to-1 MUX : 56 # XORs : 171 128-bit xor2 : 11 8-bit xor2 : 150 8-bit xor3 : 10
  • 12. Implementation Encryption Speed Software implementation (ANSI C) 27Mb/s Visual C++ 70.5Mb/s Hardware Implementation (Altra) 268Mb/s Proposed VHDL (Virtex II) 2.18Gb/s Performance Comparison
  • 13. Encryption Simulation Result
  • 14. Decryption Simulation Result
  • 15. FUTURE DEVELOPMENT • For future development, estimation on the real time required for key initialization and time for a whole encryption should be done on the real chip. • Research is still going on the encryptor core for higher bit lengths. • FPGA based solutions have shown significant speedups compared with software based approaches • The widespread adoption of distributed, wireless, and mobile computing makes the inclusion of privacy, authentication and security • Power consumption will remain a critical factor ,especially when cryptographic applications will move into embedded context
  • 16. CONCLUSION • In this paper, a VLSI implementation for the Rijndael encryption algorithm is presented • The combination of security, and high speed implementation, makes it a very good choice for wireless systems. • The whole design was captured entirely in VHDL language using a bottom-up design and verification methodology • The proposed VLSI implementation of the algorithm reduces the covered area and achieves a data throughput up to 2.18Gbit/sec. • An optimized coding for the implementation of Rijndael algorithm for 128 bits has been developed • Architectural innovations like on the fly round key generation, which facilitates simultaneous execution of sub bytes, shift rows and mix columns and round key generation has been incorporated in our coding.
  • 17. QUERRIES ? ? ?