Digital 1
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Digital 1 Presentation Transcript

  • 1. Digital Logic Circuitss Binary Logic and Gatess Logic Simulations Boolean Algebras NAND/NOR and XOR gatess Decoder fundamentalss Half Adder, Full Adder, Ripple Carry Adder
  • 2. Analog vs Digitals Analog – Continuous » Time s Every time has a value associated with it, not just some times » Magnitude s A variable can take on any value within a range » e.g. s temperature, voltage, current, weight, length, brightness, color
  • 3. Digital Systems Digital vs. Analog Waveforms +5 +5 1 0 1 V V Time Time –5 –5Digital: Analog: only assumes discrete values values vary over a broad range continuously
  • 4. Quantization
  • 5. Analog vs Digitals Digital – Discontinuous » Time (discretized) s The variable is only defined at certain times » Magnitude (quantized) s The variable can only take on values from a finite set » e.g. s Switch position, digital logic, Dow-Jones Industrial, lottery, batting-average
  • 6. Analog to Digitals A Continuous Signal is Sampled at Some Time and Converted to a Quantized Representation of its Magnitude at that Time – Samples are usually taken at regular intervals and controlled by a clock signal – The magnitude of the signal is stored as a sequence of binary valued (0,1) bits according to some encoding scheme
  • 7. Digital to Analogs A Binary Valued, B = { 0, 1 }, Code Word can be Converted to its Analog Values Output of D/A Usually Passed Through Analog Low Pass Filter to Approximate a Continuous Signals Many Applications Construct a Signal Digitally and then D/A – e.g., RF Transmitters, Signal Generators
  • 8. Digital is Ubiquitouss Electronic Circuits based on Digital Principles are Widely Used – Automotive Engine/Speed Controllers – Microwave Oven Controllers – Heating Duct Controls – Digital Watches – Cellular Phones – Video Games
  • 9. Why Digital?s Increased Noise Immunitys Reliables Inexpensives Programmables Easy to Compute Nonlinear Functionss Reproducibles Small
  • 10. Digital Design Processs Computer Aided Design Tools – Design entry – Synthesis – Verification and simulation – Physical design – Fabrication – Testing
  • 11. Definition
  • 12. Representations for combinational logics Truth tables s Exclusive-or (XOR, EXOR, not-equivalence, ring-OR)s Graphical (logic gates) s Algebraic symbol:s Algebraic equations (Boolean) s Gate symbol:
  • 13. Boolean algebra & logic circuits
  • 14. Representations of a Digital DesignTruth Tables tabulate all possible input combinations and their associated output valuesExample: half adder Example: full adder adds two binary digits adds two binary digits and to form Sum and Carry Carry in to form Sum and Carry Out A B Sum Carry A B Cin Sum Cout 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1NOTE: 1 plus 1 is 0 with a 1 1 1 1 1 carry of 1 in binary
  • 15. Representations of Digital Design: values: 0, 1 Boolean Algebra variables: A, B, C, . . ., X, Y, Z operations: NOT, AND, OR, . . . NOT X is written as X X AND Y is written as X & Y, or sometimes X Y X OR Y is written as X + YDeriving Boolean equations from truth tables: Sum = A B + A BA B Sum Carry ORd together product terms0 0 0 0 for each truth table0 1 1 0 row where the function is 11 0 1 01 1 0 1 if input variable is 0, it appears in complemented form; if 1, it appears uncomplemented Carry = A B
  • 16. Representations of a Digital Design: Boolean Algebra Another example:A B Cin Sum Cout Sum = A B Cin + A B Cin + A B Cin + A B Cin0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1 Cout = A B Cin + A B Cin + A B Cin + A B Cin
  • 17. Gate Representations of a Digital Design most widely used primitive building block in digital system design Standard Logic Gate Half Adder Schematic Representation A Inverter AND Net 1 SUM B OR Net 2 CARRY Net: electrically connected collection of wires Netlist: tabulation of gate inputs & outputs and the nets they are connected to
  • 18. Design methodology
  • 19. Top-down vs. bottom-up design
  • 20. Analysis procedures
  • 21. Schematic for 4 Bit ALUInverto rAN DGate EXO R Gate OR Gate
  • 22. Simulation of 4 Bit ALUA 4 if S=0 then D=B−A 4 D if S=1 then D=A−BB if S=2 then D=A+B 2S if S=3 then D=−A
  • 23. Elementary Binary Logic Functionss Digital circuits represent information using two voltage levels. – binary variables are used to denote these values – by convention, the values are called “1” and “0” and we often think of them as meaning “True” and “False”s Functions of binary variables are called logic functions. – AND(A,B) = 1 if A=1 and B=1, else it is zero. » AND is generally written in the shorthand A⋅B (or A&B or A∧B) – OR(A,B) = 1 if A=1 or B=1, else it is zero. » OR is generally written in the shorthand form A+B (or A|B or A∨B) – NOT(A) = 1 if A=0 else it is zero. » NOT is generally written in the shorthand form A (or ¬A or A′)s AND, OR and NOT can be used to express all other logic functions.
  • 24. Two Variable Binary Logic Functions NAND (Α⇒Β)′ EQUAL (Β⇒Α)′ EXOR ZERO Β⇒Α Α⇒Β AND NOR ONE OR A′ A B B′ A B 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 0 0 1 1 1 0 0s Can make similar truth tables for 3 variable or 4 variable functions, but gets big (256 & 65,536 columns).s Representing functions in terms of AND, OR, NOT. – NAND(A,B) = (A⋅B)′ – EXOR(A,B) = (A′⋅B) + (A⋅B ′)
  • 25. Basic Logic GatesAND Gate X X⋅Y Timing Diagram X Y Y XOR Gate X+Y X⋅Y Y X+YInverter X X’ X’ s Logic gates “compute” elementary binary functions. – output of an AND gate is “1” when both of its inputs are “1”, otherwise the output is zero – similarly for OR gate and inverter s Timing diagram shows how output values change over time as input values change
  • 26. Multivariable Gates 3 input AND Gate 6 input OR Gate A A B B A+B+C+D+E+F A⋅B⋅C C C D E Fs AND function on n variables is “1” if and only if ALL its arguments are “1”. – n input AND gate output is “1” if all inputs are “1”s OR function on n variables is “1” if and only if at least one of its arguments is “1”. – n input OR gate output is “1” if any inputs are “1”s Can construct “large” gates from 2 input gates. – however, large gates can be less expensive than required number of 2 input gates
  • 27. Elements of Boolean Algebras Boolean algebra defines rules for manipulating symbolic binary logic expressions. – a symbolic binary logic expression consists of binary variables and the operators AND, OR and NOT (e.g. A+B⋅C′)s The possible values for any Boolean expression can be tabulated in a truth table. A B C B⋅C′ A+B⋅C′s Can define circuit for 0 0 0 0 0 expression by combining 0 0 1 0 0 gates. 0 1 0 1 1 0 1 1 0 0 1 0 0 0 1 A 1 0 1 0 1 B A+B⋅C′ 1 1 0 1 1 C 1 1 1 0 1
  • 28. Schematic Capture & Logic Simulation wires advance gates simulation signal waveforms terminalsschematicentry tools signal names
  • 29. Boolean Functions to Logic Circuitss Any Boolean expression can be converted to a logic circuit made up of AND, OR and NOT gates. step 1: add parentheses to expression to fully define order of operations - A+(B⋅(C ′)) step 2: create gate for “last” operation in expression gate’s output is value of expression gate’s inputs are expressions combined by operation A A+B⋅C′ (B⋅(C′)) step 3: repeat for sub-expressions and continue until dones Numberof simple gates needed to implement expression equals number of operations in expression. – so, simpler equivalent expression yields less expensive circuit – Boolean algebra provides rules for simplifying expressions
  • 30. Basic Identities of Boolean Algebra 1. X + 0 = X 2. X⋅1 = X 3. X + 1 = 1 4. X⋅0 = 0 6. X⋅X = X 5. X + X = X 8. X⋅X ’ = 0 7. X + X ’ = 1 9. (X ’)’ = X 11. X⋅Y = Y⋅X commutative10. X + Y = Y + X 13. X⋅(Y⋅Z ) = (X⋅Y )⋅Z associative12. X+(Y+Z ) = (X+Y )+Z 15. X+(Y⋅Z ) = (X+Y )⋅(X+Z ) distributive 17. (X⋅Y)’ = X ′+Y ′14. X(Y+Z ) = X⋅Y + X⋅Z DeMorgan’s16. (X + Y )′ = X ′⋅Y ′s Identities define intrinsic properties of Boolean algebra.s Useful in simplifying Boolean expressionss Note: 15-17 have no counterpart in ordinary algebra.s Parallel columns illustrate duality principle.
  • 31. Verifying Identities Using Truth Tables (X + Y )′ = X ′⋅Y ′ X+(Y⋅Z ) = (X+Y )⋅(X+Z )XY (X + Y )′ X ′⋅Y ′ XYZ Y⋅Z X+(Y⋅Z ) X+Y X+Z (X+Y )⋅(X+Z )00 1 1 000 0 0 0 0 001 0 0 001 0 0 0 1 010 0 0 010 0 0 1 0 011 0 0 011 1 1 1 1 1 100 0 1 1 1 1 101 0 1 1 1 1 110 0 1 1 1 1 111 1 1 1 1 1s Can verify any logical equation with small number of variables using truth tables.s Break large expressions into parts, as needed.
  • 32. DeMorgan’s Law
  • 33. DeMorgan’s Laws for n Variabless We can extend DeMorgan’s laws to 3 variables by applying the laws for two variables. (X + Y + Z )′= (X + (Y + Z ))′ - by associative law = X ′⋅(Y + Z )′ - by DeMorgan’s law = X ′⋅(Y ′⋅Z ′) - by DeMorgan’s law = X ′⋅Y ′⋅Z ′ - by associative law (X⋅Y⋅Z)′ = (X⋅(Y⋅Z ))′ - by associative law = X ′ + (Y⋅Z )′ - by DeMorgan’s law = X ′ + (Y ′ + Z ′) - by DeMorgan’s law = X′ + Y ′ + Z′ - by associative laws Generalization to n variables. – (X1 + X2 + ⋅ ⋅ ⋅ + Xn)′ = X ′1⋅X ′2 ⋅ ⋅ ⋅ X ′n – (X1⋅X2 ⋅ ⋅ ⋅ Xn)′ = X ′1 + X ′2 + ⋅ ⋅ ⋅ + X ′n
  • 34. Simplification of Boolean Expressions X Y Z F=X ′YZ +X ′YZ ′+XZ by identity 14 X Y F=X ′Y(Z +Z ′)+XZ Z by identity 7 X F=X ′Y⋅1+XZ Y =X ′Y +XZ by identity 2 Z
  • 35. The Duality Principles The dual of a Boolean expression is obtained by interchanging all ANDs and ORs, and all 0s and 1s. – example: the dual of A+(B⋅C ′)+0 is A⋅(B+C ′)⋅1s The duality principle states that if E1 and E2 are Boolean expressions then E1= E2 ⇔ dual (E1)=dual (E2) where dual(E) is the dual of E. For example, A+(B⋅C ′)+0 = (B ′⋅C )+D ⇔ A⋅(B+C ′)⋅1 = (B ′+C )⋅D Consequently, the pairs of identities (1,2), (3,4), (5,6), (7,8), (10,11), (12,13), (14,15) and (16,17) all follow from each other through the duality principle.
  • 36. The Consensus TheoremTheorem. XY + X ′Z +YZ = XY + X ′ZProof. XY + X ′Z +YZ = XY + X ′Z + YZ(X + X ′) 2,7 = XY + X ′Z + XYZ + X ′YZ 14 = XY + XYZ + X ′Z + X ′YZ 10 = XY(1 + Z ) + X ′Z(1 + Y ) 2,14 = XY + X ′Z 3,2Example. (A + B )(A′ + C ) = AA′ + AC + A′B + BC = AC + A′B + BC = AC + A′BDual. (X + Y )(X ′ + Z )(Y + Z ) = (X + Y )(X ′ + Z )
  • 37. Taking the Complement of a FunctionMethod 1. Apply DeMorgan’s Theorem repeatedly. (X(Y ′Z ′ + YZ ))′ = X ′ + (Y ′Z ′ + YZ )′ = X ′ + (Y ′Z ′)′(YZ )′ = X ′ + (Y + Z )(Y ′ + Z ′)Method 2. Complement literals and take dual (X (Y ′Z ′ + YZ ))′= dual (X ′(YZ + Y ′Z ′)) = X ′ + (Y + Z )(Y ′ + Z ′)
  • 38. Sum of Products Forms The sum of products is one of two standard forms for Boolean expressions. 〈sum-of-products-expression〉 = 〈term〉 + 〈term〉 ... + 〈term〉 〈 term〉 = 〈literal〉 ⋅ 〈literal〉 ⋅ ⋅⋅⋅ ⋅ 〈literal〉 Example. X ′Y ′Z + X ′Z + XY + XYZs A minterm is a term that contains every variable, in either complemented or uncomplemented form. Example. in expression above, X ′Y ′Z is minterm, but X ′Z is nots A sum of minterms expression is a sum of products expression in which every term is a minterm Example. X ′Y ′Z + X ′YZ + XYZ ′ + XYZ is sum of minterms expression that is equivalent to expression above
  • 39. Product of Sums Forms The product of sums is the second standard form for Boolean expressions. 〈product-of-sums-expression〉 = 〈s-term〉 ⋅ 〈s-term〉 ... ⋅ 〈s-term〉 〈 s-term〉 = 〈literal〉 + 〈literal〉 + ⋅⋅⋅ + 〈literal〉 Example. (X ′+Y ′+Z )(X ′+Z )(X +Y )(X +Y +Z )s A maxterm is a sum term that contains every variable, in complemented or uncomplemented form. Example. in exp. above, X ′+Y ′+Z is a maxterm, but X ′+Z is nots A product of maxterms expression is a product of sums expression in which every term is a maxterm Example. (X ′+Y ′+Z )(X ′+Y+Z )(X+Y+Z ′)(X+Y+Z ) is product of maxterms expression that is equivalent to expression above
  • 40. NAND and NOR Gates NAND Gate X (X⋅Y)′ NOR Gate X (X+Y)′ Y Ys In certain technologies (including CMOS), a NAND (NOR) gate is simpler & faster than an AND (OR) gate.s Consequently circuits are often constructed using NANDs and NORs directly, instead of ANDs and ORs.s Alternative gate representations makes this easier. = = = =
  • 41. Exclusive Or and Odd FunctionA Alternative Implementation EXOR gate A AB ′ +A′BB Bs The EXOR function is defined by A⊕B = AB ′ + A′B.s The odd function on n variables is 1 when an odd number of its variables are 1. – odd(X,Y,Z ) = XY ′Z ′+ X ′Y Z ′ + X ′Y ′Z + X Y Z = X ⊕Y ⊕Z – similarly for 4 or more variabless Parity checking circuits use the odd function to provide a simple integrity check to verify correctness of data. – any erroneous single bit change will alter value of odd function, allowing detection of the change
  • 42. Positive and Negative Logics In positive logic systems, a high voltage is associated with a logic 1, and a low voltage with a logic 0. – positive logic is just one of two conventions that can be used to associate a logic value with a voltage – sometimes it is more convenient to use the opposite conventions In logic diagrams that use negative logic, a polarity indicator is used to indicate the correct logical interpretation for a signal. X X X⋅Y X+Y Y Ys Circuits commonly use a combination of positive and negative logic.
  • 43. Analysis example
  • 44. Truth tables from logic diagram
  • 45. Logic simulation
  • 46. Decoder Fundamentalss Route data to one specific output line.s Selection of devices, resourcess Code conversions.s Arbitrary switching functions – implements the AND planes Asserts one-of-many signal; at most one output will be asserted for any input combination
  • 47. Encoding Binary Decimal Unencoded Encoded 0 0001 00 1 0010 01 2 0100 10 3 1000 11Note: Finite state machines may be unencoded ("one-hot") or binary encoded. If the all 0s state is used, then one less bit is needed and it is called modified one-hot coding.
  • 48. Why Encode? A Logarithmic Relationship 8 7 6 5Log2(N) 4 3 2 1 0 0 25 50 75 100 125 150 N
  • 49. 2:4 Decoder A B AND 2 Y EQ3 11 A Y B AND 2 A EQ2 10 A Y B AND 2 A EQ1 01D0 A Y B AND 2 B EQ0 00D1 What happens when the inputs goes from 01 to 10?
  • 50. 2:4 Decoder with Enable A B C AND 3 Y EQ3 11 A B C AND 3 A Y EQ2 10 A B C AND 3 A Y EQ1 01 A D0 B D1 C AND 3 B Y EQ0 00ENABLE
  • 51. 2:1 Multiplexer AA Y X1 B A Y Y B AS Y X2 BB
  • 52. Design synthesis procedure
  • 53. Half Adder
  • 54. Full Adder – with EXOR, AND and OR
  • 55. Full Adder – with EXOR and NANDs One-bit Full Adder (FA) s Schematic View: – 3 inputs: A, B, C – cell-based approach – 2 outputs: S, Co – Truth table: C S A, B, C S, Co B 0, 0, 0 0, 0 0, 0, 1 1, 0 0, 1, 0 1, 0 0, 1, 1 0, 1 Co A 1, 0, 0 1, 0 1, 0, 1 0, 1 1, 1, 0 0, 1 1, 1, 1 1, 1
  • 56. Ripple Carry Adder