• Save
Microcontrollermesin2008 aneukmesinunsyiah
Upcoming SlideShare
Loading in...5

Microcontrollermesin2008 aneukmesinunsyiah







Total Views
Views on SlideShare
Embed Views



0 Embeds 0

No embeds



Upload Details

Uploaded via as Adobe PDF

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
Post Comment
Edit your comment

Microcontrollermesin2008 aneukmesinunsyiah Microcontrollermesin2008 aneukmesinunsyiah Presentation Transcript

  • Relevance of Microcontrollers A white paper by Sun Microsystems claims that by the end of the decade, an average home will contain between 50 to 100 microcontrollers controlling digital phones, microwave ovens, VCRs, televisions sets and television remotes, dishwashers, home security systems, PDAs etc An average car has about 15 processors; the 1999 processors; Mercedes S-class car has 63 microprocessors, while the microprocessors, 1999 BMW has 65 processors ! Except perhaps the human body, microprocessors and microcontrollers have gotten into everything around us. us. 16-05-2013 Mahesh J. vadhavaniya 1
  • Objectives… Introduction PIC Microcontroller Development Architecture PIC18 PIC18 Architecture Features & Peripherals ARM Microcontroller Introduction to ARM Ltd Programmers Model RCT (Reverse Conducting Thyristor). Thyristor). 16-05-2013 Mahesh J. vadhavaniya 2
  • Introduction The microcontrollers played revolutionary role embedded industry after the invention of Intel 8051. 8051. in The steady and progressive research in this field gave the industry more efficient, high-performance and low-power highlowconsumption microcontrollers. microcontrollers. The AVR, PIC and ARM are the prime examples. examples. The new age microcontrollers are getting smarter and richer by including latest communication protocols like USB, I2C, SPI, Ethernet, CAN etc. etc. 16-05-2013 Mahesh J. vadhavaniya 3
  • Introduction How Many Microcontrollers !!! ??? 16-05-2013 Mahesh J. vadhavaniya 4
  • Who are ??? •Atmel •ARM •Intel •8-bit •8XC42 •MCS48 •MCS51 •8xC251 •16-bit •MCS96 •MXS296 •National Semiconductor •COP8 •Microchip •12-bit instruction PIC •14-bit instruction PIC •PIC16F84 •16-bit instruction PIC 16-05-2013 •NEC •Motorola •8-bit •68HC05 •68HC08 •68HC11 •16-bit •68HC12 •68HC16 •32-bit •683xx •Texas Instruments •TMS370 •MSP430 •Zilog •Z8 •Z86E02 Mahesh J. vadhavaniya 5
  • PIC Chip 16-05-2013 Mahesh J. vadhavaniya 6
  • PIC microcontrollers History The PIC microcontroller was developed by General Instruments in 1975. 1975. The PIC was developed when Microelectronics Division of General Instruments was testing its 16-bit CPU CP1600. 16CP1600. Although the CP1600 was a good CPU but it had low I/O CP1600 performance. performance. The PIC controller was used to offload the I/O the tasks from CPU to improve the overall performance of the system. system. In 1985, 1985, General Instruments converted Microelectronics Division to Microchip Technology. Technology. 16-05-2013 Mahesh J. vadhavaniya their 7
  • PIC microcontrollers PIC stands for Peripheral Interface Controller. Controller. The General Instruments used the acronyms Programmable Interface Controller and Programmable Intelligent Computer for the initial PICs (PIC1640 and (PIC1640 PIC1650) PIC1650). In 1993, Microchip Technology launched the 8-bit 1993, PIC16C PIC16C84 with EEPROM which could be programmed using serial programming method. method. The improved version of PIC16C84 with flash memory PIC16C (PIC18F (PIC18F84 and PIC18F84A) hit the market in 1998. PIC18F84A) 1998. 16-05-2013 Mahesh J. vadhavaniya 8
  • PIC microcontrollers Development Since 1998, Microchip Technology continuously developed 1998, new high performance microcontrollers with new complex architecture and enhanced in-built peripherals. inperipherals. PIC microcontroller is based on Harvard architecture. architecture. At present PIC microcontrollers are widely used for industrial purpose due to its high performance ability at low power consumption. consumption. It is also very famous among hobbyists due to moderate cost and easy availability of its supporting software and hardware tools like compilers, simulators, debuggers etc. etc. 16-05-2013 Mahesh J. vadhavaniya 9
  • PIC microcontrollers Development The 8-bit PIC microcontroller is divided into following four categories on the basis of internal architecture: architecture: 1. Base Line PIC 2. Mid-Range PIC Mid3. Enhanced Mid-Range PIC Mid4. PIC18 PIC18 1. Base Line PIC Base Line PICs are the least complex PIC microcontrollers. microcontrollers. These microcontrollers work on 12-bit instruction 12architecture which means that the word size of instruction sets are of 12 bits for these controllers. controllers. 16-05-2013 Mahesh J. vadhavaniya 10
  • PIC microcontrollers Development 1. Base Line PIC…cntd PIC… These are smallest and cheapest PICs, available with 6 to 40 pin packaging. packaging. The small size and low cost of Base Line PIC replaced the traditional ICs like 555, logic gates etc. in industries. 555, etc. industries. 2. Mid - Range PIC MidMid-Range PICs are based on 14-bit instruction 14architecture and are able to work up to 20 MHz speed. speed. These controllers are available with 8 to 64 pin packaging. packaging. 16-05-2013 Mahesh J. vadhavaniya 11
  • PIC microcontrollers Development 2. Mid - Range PIC… cntd PIC… These microcontrollers are available with different peripherals like ADC, PWM, Op-Amps and different communication protocols Oplike USART, SPI, I2C (TWI), etc. which make them widely usable etc. microcontrollers not only for industry but for hobbyists as well. well. 3. Enhanced Mid - Range PIC These controllers are enhanced version of Mid-Range core. Midcore. This range of controllers provides additional performance, greater flash memory and high speed at very low power consumption. consumption. This range of PIC also includes multiple peripherals and supports protocols like USART, SPI, I2C and so on. on. 16-05-2013 Mahesh J. vadhavaniya 12
  • PIC microcontrollers Development 4. PIC 18 PIC18 PIC18 range is based on 16-bit instruction architecture 16incorporating advanced RISC architecture which makes it highest performer among the all 8-bit PIC families. families. The PIC18 range is integrated with new age PIC18 communication protocols like USB, CAN, LIN, Ethernet (TCP/IP protocol) to communicate with local and/or internet based networks. networks. This range also supports the connectivity of Human Interface Devices like touch panels etc. etc. 16-05-2013 Mahesh J. vadhavaniya 13
  • PIC microcontrollers 8-64 Enhanced MidRange 8-64 18-100 Up to 3 KB Up to 14 KB Up to 28 KB Up to 128 KB Data Memory Up to 134 Bytes Up to 368 Bytes Up to 1.5 KB Up to 4 KB Instruction Length 12-bit 14-bit 14-bit 16-bit No. of instruction set 33 35 49 83 Speed 5 MIPS* 5 MIPS In addition of baseline · SPI · I2C · UART · PWM · 10-bit ADC · OP-Amps 8 MIPS Up to 16 MIPS In addition of Enhanced Midrange • CAN • LIN • USB • Ethernet • 12-bit ADC Base Line No. of Pins Program Memory Mid-Range 6-40 Feature • Comparator • 8-bit ADC • Data Memory •Internal Oscillator Families PIC10,PIC12, PIC16 16-05-2013 PIC12, PIC16 *MIPS stand for Millions of Instructions per Second Mahesh J. vadhavaniya In addition of Midrange · High Performance · Multiple communication peripherals PIC12F1XXX, PIC16F1XXX PIC18 PIC18 14
  • PIC microcontrollers 16-05-2013 Mahesh J. vadhavaniya 15
  • PIC microcontrollers Development Besides 8-bit microcontrollers, Microchip also manufactures 16-bit and 32-bit microcontrollers. Recently 1632microcontrollers. Microchip developed XLP (Extreme Low Power) series microcontrollers which are based on NanoWatt technology. technology. These controllers draw current in order of nanoamperes(nA). nanoamperes(nA) Memory variations The PIC microcontrollers are available with different memory options which are mask ROM, EPROM and flash memory. memory. They are denoted with different symbols as given in the following table: table: 16-05-2013 Mahesh J. vadhavaniya 16
  • PIC microcontrollers Development Memory variations Symbol Memory Type Example C EPROM PIC16Cxxx CR Mask ROM PIC16CRxxx F Flash memory PIC16Fxxx PIC microcontrollers are also available with extended voltage ranges which reduce the frequency range. range. The operating voltage range of these PICs is 2.0-6.0 volts. volts. The letter ‘L’ is included in controller’s name to denote extended voltage range controllers. For example, PIC16LFxxx controllers. PIC16LFxxx (Operating voltage 2.0-6.0 volts). volts). 16-05-2013 Mahesh J. vadhavaniya 17
  • PIC microcontrollers Architecture PIC microcontrollers are based on advanced RISC architecture. architecture. RISC stands for Reduced Instruction Set Computing. Computing. In this architecture, the instruction set of hardware gets reduced which increases the execution rate (speed) of system. system. PIC microcontrollers follow Harvard architecture for internal data transfer. transfer. In Harvard architecture there are two separate memories for program and data. data. These two memories are accessed through different buses for data communication between memories and CPU core. core. 16-05-2013 Mahesh J. vadhavaniya 18
  • PIC microcontrollers Architecture This architecture improves the speed of system over Von Neumann architecture in which program and data are fetched from the same memory using the same bus. bus. PIC18 PIC18 series controllers are based on 16-bit instruction set. 16set. The question may arise that if PIC18 are called 8-bit PIC18 microcontrollers, then what about them being based on 16-bit 16instructions set. set. ‘PIC18 ‘PIC18 is an 8-bit microcontroller’ this statement means that the CPU core can receive/transmit or process a maximum of 8-bit data at a time. time. 16-05-2013 Mahesh J. vadhavaniya 19
  • PIC microcontrollers Architecture On the other hand the statement ‘PIC18 microcontrollers ‘PIC18 are based on 16-bit instruction set’ means that the assembly 16instruction sets are of 16-bit. 16-bit. The data memory is interfaced with 8-bit bus and program memory is interfaced with 16-bit bus as depicted in the 16following figure. figure. 16-05-2013 Mahesh J. vadhavaniya 20
  • PIC microcontrollers Architecture Von Neumann Architecture: Architecture: • Fetches instructions and data from a single memory space • Limits operating bandwidth Harvard Architecture: Architecture: • Uses two separate memory spaces for program instructions and data • Improved operating bandwidth • Allows for different bus widths 16-05-2013 Mahesh J. vadhavaniya 21
  • PIC microcontrollers PIC18 PIC18 Harvard Architecture PIC microcontroller contains an 8-bit ALU (Arithmetic Logic Unit) and an 8-bit Working Register (Accumulator). (Accumulator). There are different GPRs (General Purpose Registers) and SFRs (Special Function Registers) in a PIC microcontroller. microcontroller. The overall system performs 8-bit arithmetic and logic functions. functions. These functions usually need one or two operands. operands. One of the operands is stored in WREG (Accumulator) and the other one is stored in GPR/SFR. GPR/SFR. The two data is processed by ALU and stored in WREG or other registers 16-05-2013 Mahesh J. vadhavaniya 22
  • PIC microcontrollers PIC18 PIC18 Harvard Architecture 16-05-2013 Mahesh J. vadhavaniya 23
  • PIC microcontrollers PIC18 PIC18 Harvard Architecture The process occurs in a single machine cycle. cycle. In PIC microcontroller, a single machine cycle consists of 4 oscillation periods. periods. Thus an instruction needs 4 clock periods to be executed. executed. This makes it faster than other 8051 microcontrollers. microcontrollers. This makes it faster than other 8051 microcontrollers. microcontrollers. Pipelining Early processors and controllers could fetch or execute a single instruction in a unit of time. time. The PIC microcontrollers are able to fetch and execute the instructions in the same unit of time thus increasing their instruction throughput. throughput. 16-05-2013 Mahesh J. vadhavaniya 24
  • PIC microcontrollers PIC18 PIC18 Harvard Architecture Pipelining This technique is known as instruction pipelining where the processing of instructions is split into a number of independent steps. steps. 16-05-2013 Mahesh J. vadhavaniya 25
  • PIC microcontrollers Features C Compiler Optimized Architecture with Optional Extended Instruction Set 100, 100,000 Erase/Write Cycle Enhanced Flash Program Memory Typical 1,000,000 Erase/Write Cycle Data EEPROM Memory 000, Typical Flexible oscillator option Four Crystal modes, including High-Precision PLL for USB HighTwo External Clock modes, Up to 48 MHz Internal Oscillator: 8 user-selectable frequencies, from 31 kHz Oscillator: userto 8 MHz Dual Oscillator Options allow Microcontroller and USB module to Run at different Clock Speeds 16-05-2013 Mahesh J. vadhavaniya 26
  • PIC microcontrollers Peripherals I/O Ports : PIC18F PIC18F4550 have 5 (Port A, Port B, Port C, Port D and Port E) 8-bit input-output ports. inputports. PortB & PortD have 8 I/O pins each. each. Although other three ports are 8-bit ports but they do not have eight I/O pins. pins. Although the 8-bit input and output are given to these ports, but the pins which do not exist, are masked internally. internally. Memory : PIC18F PIC18F4550 consists of three different memory sections. sections. 16-05-2013 Mahesh J. vadhavaniya 27
  • PIC microcontrollers Peripherals 1. Flash Memory: Memory: Flash memory is used to store the program downloaded by a user on to the microcontroller. microcontroller. Flash memory is non-volatile, i.e., it retains the program noneven after the power is cut-off. cut-off. PIC18F PIC18F4550 has 32KB of Flash Memory. 32KB Memory. 2. EEPROM: EEPROM: This is also a nonvolatile memory which is used to store data like values of certain variables. variables. PIC18F PIC18F4550 has 256 Bytes of EEPROM. EEPROM. 16-05-2013 Mahesh J. vadhavaniya 28
  • PIC microcontrollers Peripherals 3. SRAM: SRAM: Static Random Access Memory is the volatile memory of the microcontroller, i.e., it loses its data as soon as the power is cut off PIC18F PIC18F4550 is equipped with 2 KB of internal SRAM. . SRAM. Oscillator : The PIC18F series has flexible clock options. PIC18F options. An external clock of up to 48 MHz can be applied to this series. series. These controllers also consist of an internal oscillator which provides eight selectable frequency options varying from 31 KHz to 8 MHz. MHz. 16-05-2013 Mahesh J. vadhavaniya 29
  • PIC microcontrollers Peripherals 8 x 8 Multiplier : The PIC18F4550 includes an 8 x 8 multiplier hardware. PIC18F hardware. This hardware performs the multiplications in single machine cycle. cycle. This gives higher computational throughput and reduces operation cycle & code length. length. ADC Interface : PIC18F PIC18F4550 is equipped with 13 ADC (Analog to Digital Converter) channels of 10-bits resolution. 10resolution. 16-05-2013 Mahesh J. vadhavaniya 30
  • PIC microcontrollers Peripherals Timers / Counters : PIC18F PIC18F4550 has four timer/counters. timer/counters. There is one 8-bit timer and the remaining timers have option to select 8 or 16 bit mode. mode. Interrupts : PIC18F PIC18F4550 consists of three external interrupts sources. sources. There are 20 internal interrupts which are associated with different peripherals like USART, ADC, Timers, and so on. on. 16-05-2013 Mahesh J. vadhavaniya 31
  • PIC microcontrollers PIN Diagram 16-05-2013 Mahesh J. vadhavaniya 32
  • PIC microcontrollers PIN Description Pin No. Name Description Alternate Function 1 MCLR/VPP/RE3 Master clear Vpp: programming voltage input RE3: I/O pin of PORTE, PIN 3 2 RA0/AN0 AN0: Analog input 0 3 RA1/AN1 AN1: Analog input 1 4 RA2/AN2/VREF-/CVREF 5 RA3/AN3/VREF+ AN2: Analog input 2 VREF-: A/D reference voltage (low) input. CVREF: Analog comparator reference output. 6 7 RA4/T0CKI/C1OUT/RCV RA5/AN4/SS/HLVDIN/C2OUT 16-05-2013 Port A I/O Pins 1-6 AN3: Analog input3 VREF+: A/D reference voltage (high) input T0CKI: Timer0 external clock input. C1OUT: Comparator 1 output RCV: External USB transceiver RCV input. AN4: Analog input 4 SS: SPI slave select input HLDVIN: High/Low-Voltage Detect input. C2OUT: Comparator 2 output. Mahesh J. vadhavaniya 33
  • PIC microcontrollers PIN Description Pin No. Name 8 RE0/AN5/CK1SPP 9 RE1/AN6/CK2SPP 10 RE2/AN7/OESPP 11 VDD Positive supply 12 Vss Ground 13 OSC1/CLKI Oscillator pin 1 CLKI: External clock source input 14 OSC2/CLKO/RA6 Port E I/O Pin 7 CLKO: External clock source output OSC2: Oscillator pin 2 16-05-2013 Description Alternate Function AN5: Analog input 5 CK1SPP: SPP clock 1 output. Port E I/O Pins 1-3 AN6: Analog input 6 CK2SPP: SPP clock 2 output AN6: Analog input 7 OESPP : SPP Enabled output Mahesh J. vadhavaniya 34
  • PIC microcontrollers PIN Description Pin No. Name 15 RC0/T1OSO/T13CKI 16 RC1/T1OSI/CCP2/UOE 17 VUSB 19 RD1/SPP1 21 RD2/SPP2 22 Port C I/O Pins 1-3 T1OSI: Timer1 oscillator output CCP2:Capture 2 input/Compare 2 output/PWM2 output UOE: External USB transceiver OE output CCP1: Capture 1 input/Compare 1 output/PWM1 output. P1A :Enhanced CCP1 PWM output, channel A. RD0/SPP0 20 Alternate Function T1OSO :Timer1 oscillator output T13CKI: Timer1/Timer3 external clock input. RC2/CCP1/P1A 18 Description RD3/SPP3 16-05-2013 Internal USB 3.3V voltage regulator output, positive supply for the USB transceiver. Port D I/O Pins 1-4 SPP0-SPP4 Streaming Parallel Port data Mahesh J. vadhavaniya 35
  • PIC microcontrollers PIN Description Pin No. Name 23 RC3/D-/VM Description Port C I/O Pins 4-5 Alternate Function D-: USB differential minus line (input/output) VM: External USB transceiver VM input. 24 RC4/D+/VP D+: USB differential plus line (input/output). VP: External USB transceiver VP input. 25 RC6/TX/CK TX: EUSART asynchronous transmit. CK: EUSART synchronous clock (see RX/DT). Port C I/O Pins 7-8 26 RC7/RX/DT/SDO 27 RD4/SPP4 28 RD5/SPP5/P1B 29 RD6/SPP6/P1C 30 RD7/SPP7/P1D 16-05-2013 RX: EUSART asynchronous receive. DT: EUSART synchronous data (see TX/CK). SDO: SPI data out. SPP4:Streaming Parallel Port data SPP5:Streaming Parallel Port data P1B: Enhanced CCP1 PWM output, channel B Port D I/O Pins 5-8 SPP6:Streaming Parallel Port data P1C: Enhanced CCP1 PWM output, channel C SPP7:Streaming Parallel Port data P1D: Enhanced CCP1 PWM output, channel D Mahesh J. vadhavaniya 36
  • PIC microcontrollers PIN Description Pin No. 31 32 33 Name Description Vss VDD Ground Positive supply AN12: Analog input 12. INT0: External interrupt 0. FLT0: Enhanced PWM Fault input (ECCP1 module). SDI: SPI data in. SDA: I2C data I/O. RB0/AN12/INT0/FLT0/SDI/S DA Port B I/O Pins 1-8 34 35 Alternate Function RB1/AN10/INT1/SCK/SCL RB2/AN8/INT2/VMO 16-05-2013 AN10: Analog input 10. INT1: External interrupt 1. SCK: Synchronous serial clock input/output for SPI mode. SCL: Synchronous serial clock input/output for I2C mode. AN8: Analog input 8. INT2: External interrupt 2. VMO: External USB transceiver VMO output. Mahesh J. vadhavaniya 37
  • PIC microcontrollers PIN Description Pin No. 36 37 Name Description AN9: Analog input 9. CCP2: Capture 2 input/Compare 2 output/PWM2 output. VPO: External USB transceiver VPO output. RB3/AN9/CCP2/VPO AN11: Analog input 11. KBI0: Interrupt-on-change pin. CSSPP: SPP chip select control output. RB4/AN11/KBI0/CSSPP 38 39 40 16-05-2013 RB5/KBI1/PGM Alternate Function Port B I/O Pins 1-8 KBI1: Interrupt-on-change pin. PGM: Low-Voltage ICSP Programming enable pin. RB6/KBI2/PGC KBI2: Interrupt-on-change pin. PGC: Low-Voltage ICSP Programming enable pin. RB7/KBI3/PGD KBI3: Interrupt-on-change pin. PGD: In-Circuit Debugger and ICSP programming data pin. Mahesh J. vadhavaniya 38
  • PIC microcontrollers Block Diagram 16-05-2013 Mahesh J. vadhavaniya 39
  • PIC microcontrollers Arithmetic Logic Unit (ALU) Instruction decoder 16-bit instructions 16Status register that stores flags 5-bits WREG – working register 8-bit accumulator Microprocessor Unit Registers Program Counter (PC) 21-bit register that holds the Program Memory address 21Bank Select Register (BSR) 4-bit register used in direct addressing the Data Memory File Select Registers (FSRs) 12-bit registers used as memory pointers in indirect 12addressing Data Memory 16-05-2013 Mahesh J. vadhavaniya 40
  • PIC microcontrollers Address bus 21-bit address bus for Program Memory 21Addressing capacity: 2 MB capacity: 12-bit address bus for Data Memory 12Addressing capacity: 4 KB capacity: Microprocessor Unit Data bus 16-bit instruction/data bus for Program Memory 168-bit data bus for Data Memory PIC18F452/ PIC18F452/4520 Memory Program Memory: 32 K (Address range: 000000 to 007FFFH) Memory: range: 007FFFH) Data Memory: 4 K (Address range: 000 to FFFH) Memory: range: Data EEPROM Not part of the data memory space Addressed through special function registers 16-05-2013 Mahesh J. vadhavaniya 41
  • PIC microcontrollers Special Features Sleep mode PowerPower-down mode Microprocessor Unit Watchdog timer (WDT) Able to reset the processor if the program is caught in unknown state (e.g., infinite loop) (e. Code protection EEPROM can be protected through SFR In-circuit serial programming InIn-circuit debugger In16-05-2013 Mahesh J. vadhavaniya 42
  • PIC18F PIC18F4X2 Architecture Block Diagram 16-05-2013 Mahesh J. vadhavaniya 43
  • Embedded System MicrocontrollerMicrocontroller-based Time and Temperature System 16-05-2013 Mahesh J. vadhavaniya 44
  • 16-05-2013 Mahesh J. vadhavaniya 45
  • T H E A R C H I T E C T U R E F O R T TM H E D I G I T A L W O R 47L D
  • The ARM Architecture T H E A R C H I T E C T U R E F O R T TM H E D I G I T A L W O R 48L D
  • ARM The ARM is a 32-bit Reduced 32Instruction Set Computer (RISC) RISC) Instruction Set Architecture (ISA) ISA) developed by ARM Holdings. Holdings. It was known as the Advanced RISC Machine. Machine. 16-05-2013 Mahesh J. vadhavaniya 48
  • ARM Ltd Founded in November 1990. 1990. Spun out of Acorn Computers. Computers. Designs the ARM processor cores. cores. range of RISC Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers. customers. ARM does not fabricate silicon itself. itself. Also develop technologies to assist with the design-in of the ARM architecture designSoftware tools, boards, debug hardware, application software, bus architectures, peripherals etc 16-05-2013 Mahesh J. vadhavaniya 49
  • Licencable Architecture Companies that are currently or formerly ARM licensees include : Alcatel, Apple Inc., Atmel, Broadcom, Cirrus Logic, Digital Inc. Equipment Corporation, Freescale, Intel (through DEC), Freescale, LG, Marvell Technology Group, NEC, NVIDIA, NXP (previously Philips), Oki, Qualcomm, Samsung, Sharp, ST Microelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha and ZiiLABS 16-05-2013 Mahesh J. vadhavaniya 50
  • ARM Partnership Model 16-05-2013 Mahesh J. vadhavaniya 51
  • Introduction Leading provider of 32-bit 32microprocessors, 75% of market. 75% market. High performance Low power consumption Low system cost embedded RISC Solutions for Embedded real-time systems for mass storage, realautomotive, industrial and networking applications. applications. Secure applications - smartcards and SIMs Open platforms running complex operating systems Low system cost 16-05-2013 Mahesh J. vadhavaniya 52
  • Introduction ARMv1 ARMv1 First version of ARM processor 26-bit addressing, no multiply / coprocessor 26ARMv2 ARMv2 First commercial chip Included 32-bit result multiply instructions/coprocessor 32support ARMv2 ARMv2a ARM3 ARM3 chip with on-chip cache onAdded load and store cache management ARMv3 ARMv3 ARM6 ARM6, 32 bit addressing, virtual memory support. support. 16-05-2013 Mahesh J. vadhavaniya 53
  • Development of the ARM Architecture 1 2 Halfword and signed halfword / byte support System mode 4 SA-110 3 Early ARM architectures ARM7TDMI ARM720T 16-05-2013 5TE CLZ SA-1110 Thumb instruction set Improved ARM/Thumb Interworking Saturated maths DSP multiplyaccumulate instructions ARM1020E 4T XScale ARM9TDMI ARM940T ARM9E-S ARM966E-S Mahesh J. vadhavaniya Jazelle 5TEJ Java bytecode execution ARM9EJ-S ARM926EJ-S ARM7EJ-S ARM1026EJ-S SIMD Instructions 6 Multi-processing V6 Memory architecture (VMSA) Unaligned data support ARM1136EJ-S 54
  • ARM Processor Core Current low-end ARM core for applications like digital lowmobile phones. phones. TDMI T: Thumb, 16-bit instruction set 16D: on-chip Debug support, enabling the processor to onhalt in response to a debug request M: enhanced Multiplier, yield a full 64-bit result, high 64performance I: Embedded ICE hardware Von Neumann architecture 3-stage pipeline 16-05-2013 Mahesh J. vadhavaniya 55
  • ARM Core Diagram 16-05-2013 Mahesh J. vadhavaniya 56
  • The Registers ARM has 37 registers all of which are 32-bits long 321 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers The current processor mode governs which of several banks is accessible. Each mode can access accessible. a particular set of r0-r12 registers a particular r13 (the stack pointer, sp) and r14 (the link register) the program counter, r15 (pc) the current program status register, cpsr Privileged modes (except System) can also access a particular spsr (saved program status register) 16-05-2013 Mahesh J. vadhavaniya 57
  • Different States When the processor is executing in ARM state : All instructions are 32 bits wide All instructions must be word aligned When the processor is executing in Thumb state : All instructions are 16 bits wide All instructions must be halfword aligned When the processor is executing in Jazelle state : All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once 16-05-2013 Mahesh J. vadhavaniya 58
  • Thumb Thumb is a 16-bit instruction set 16Optimised for code density from C code (~65% of ARM (~65% code size) Improved performance from narrow memory Subset of the functionality of the ARM instruction set Core has additional execution state – Thumb Switch between ARM and Thumb using BX instruction 31 0 ADDS r2,r2,#1 32-bit ARM Instruction 1 5 ADD r2,#1 0 For most instructions generated by compiler : Conditional execution is not used Source and destination registers identical Only Low registers used Constants are of limited size Inline barrel shifter not used 16-bit Thumb Instruction 16-05-2013 Mahesh J. vadhavaniya 59
  • ARM Interface Signals cl ock control co nfiguration in terrupts in itialization bu s control de bug co processor interface po wer 16-05-2013 A[31:0] mclk wait eclk Din[31:0] Dout[31:0] bigend irq ¼q isync D[31:0] bl[3:0] r /w mas[1:0] mreq seq lock reset enin enout enouti abe ale ape dbe tbe busen highz busdis ecapclk trans mode abort [4:0] me mory interface MMU interface Tbit dbgrq breakpt dbgack exec extern1 extern0 dbgen rangeout0 rangeout1 dbgrqi commrx commtx opc cpi cpa cpb Vdd Vss Mahesh J. vadhavaniya TAP information bo undary scan extension TRST TCK TMS TDI TDO core tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] drivebs ecapclkbs icapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs ARM7TDMI st ate JTAG controls 60
  • ARM Interface Signals Clock control All state change within the processor are controlled by mclk, mclk, the memory clock Internal clock = mclk AND wait eclk clock output reflects the clock used by the core Memory interface 32-bit address A[31:0], bidirectional data bus D[31:0], 32A[31: D[31: separate data out Dout[31:0], data in Din[31:0] Dout[31: Din[31: seq indicates that the memory address will be sequential to that used in the previous cycle mre q 0 0 1 1 16-05-2013 s eq 0 1 0 1 Cy c l e N S I C Us e Non-sequential memory access Sequential memory access Internal cycle – bus and memory inactive Coprocessor register transfer – memory inactive Mahesh J. vadhavaniya 61
  • ARM Interface Signals Initialization fiq, fast interrupt request, higher priority fiq, irq, normal interrupt request irq, isync, isync, allow the interrupt synchronizer to be passed Interrupt reset, starts the processor from a known state, executing from address 0000000016 ARM Characteristics Process M etal layers Vdd 16-05-2013 0.35 um 3 3.3 V Transistors Core area Clock 74,209 2 2.1 mm 0 to 66 M Hz Mahesh J. vadhavaniya M IPS Power M IPS/W 60 87 mW 690 62
  • Memory Access The ARM is a Von Neumann, load/store architecture, i.e., Only 32 bit data bus for both inst. inst. and data. data. Only the load/store inst. (and inst. SWP) access memory Memory is addressed as a 32 bit address space Data type can be 8 bit (bytes), 16 bit (half(half-words) or 32 bit (words), and may be seen as a byte line folded into 4-byte words 16-05-2013 Mahesh J. vadhavaniya 63
  • Processor Core Vs CPU Core Processor Core The engine that fetches instructions and execute them E.g.: ARM7TDMI, ARM9TDMI, ARM9E-S ARM7 ARM9 ARM9 16-05-2013 virtual address MMU instruction & data cache physical address CPU Core Consists of the ARM processor core and some tightly coupled function blocks Cache and memory management blocks E.g.: ARM710T, ARM710T, ARM720T, ARM720T, ARM74T, ARM74T, ARM920T, ARM920T, ARM922T, ARM922T, ARM940T, ARM946E ARM940T, ARM946E-S, and ARM966E-S ARM966E ARM7TDMI EmbeddedICE & JTAG instructions & data write buffer CP15 AMBA interface AMBA AMBA address data Mahesh J. vadhavaniya ARM710T 64
  • ARM Powered Products 16-05-2013 Mahesh J. vadhavaniya 65
  • Intellectual Property ARM provides hard and soft views to licencees RTL and synthesis flows GDSII layout Licencees have the right to use hard or soft views of the IP soft views include gate level netlists hard views are DSMs OEMs must use hard views to protect ARM IP 16-05-2013 Mahesh J. vadhavaniya 66
  • Data Sizes and Instruction Sets The ARM is a 32-bit architecture. 32- architecture. When used in relation to the ARM: ARM: Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes) Most ARM’s implement two instruction sets : 32-bit ARM Instruction Set 3216-bit Thumb Instruction Set 16Jazelle cores can also execute Java byte code. code. 16-05-2013 Mahesh J. vadhavaniya 67
  • Processor Modes The ARM has seven basic operating modes : User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode 16-05-2013 Mahesh J. vadhavaniya 68
  • The ARM Register Set Current Visible Registers Abort Mode SVC Mode Undef Mode IRQ Mode FIQ Mode User Mode r0 r1 r2 r3 r4 r5 r6 r7 Banked out Registers User FIQ r8 r9 r10 r11 r8 r9 r10 r11 r8 r9 r10 r11 r12 r13 (sp) r12 r13 (sp) r14 (lr) r14 (lr) r15 (pc) cpsr spsr 16-05-2013 IRQ SVC Undef Abort r12 r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) spsr spsr spsr spsr spsr Mahesh J. vadhavaniya 69
  • Register Organization Summary User r0 r1 r2 r3 r4 r5 r6 FIQ User mode r0-r7, r15, and cpsr IRQ User mode r0-r12, r15, and cpsr SVC Undef User mode r0-r12, r15, and cpsr User mode r0-r12, r15, and cpsr Abort User mode r0-r12, r15, and cpsr r7 r8 r9 r10 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r11 r12 r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) spsr spsr spsr spsr Thumb state Low registers spsr Thumb state High registers r15 (pc) cpsr Note: System mode uses the User mode register set 16-05-2013 Mahesh J. vadhavaniya 70
  • 16-05-2013 Mahesh J. vadhavaniya 71
  • ARM 7 applications 16-05-2013 Mahesh J. vadhavaniya 72
  • ARM 9 applications 16-05-2013 Mahesh J. vadhavaniya 73
  • ARM 11 applications 16-05-2013 Mahesh J. vadhavaniya 74
  • ARM Cortex M applications Dell E4300 Latitude Laptop. Laptop. instant boot-up for users bootand access to select applications, with multi-day multibattery lifetimes. lifetimes. 16-05-2013 Mahesh J. vadhavaniya 75
  • ARM Cortex A applications 16-05-2013 Mahesh J. vadhavaniya 76
  • ARM Cortex R 16-05-2013 Mahesh J. vadhavaniya 77
  • Architectures overview 16-05-2013 Mahesh J. vadhavaniya 78
  • ARM 7 (ARM7-TDMI-S) 16-05-2013 Mahesh J. vadhavaniya 79
  • ARM7 TDMITDMI-S NXP LPC2148 16-05-2013 Mahesh J. vadhavaniya 80
  • ARM CortexR 16-05-2013 Mahesh J. vadhavaniya 81
  • TEXAS INSTRUMENTS TI MSP430 16-05-2013 Mahesh J. vadhavaniya 82
  • MSP 430 MixedMixed-signal microcontroller family. family. 16-bit CPU. 16- CPU. Low cost, low power consumption. consumption. Metering, wireless radio frequency engineering (RF), etering, batterybattery-powered applications. applications. MSP430x MSP430x1xx - MSP430x5xx Series. MSP430x Series. Von Neumann architecture. architecture. 16 x 16 bit registers (including PC, SP, SR, constant generator). generator). Simple instruction set. set. 20 bit address extension. extension. 16-05-2013 Mahesh J. vadhavaniya 83
  • Peripherals GeneralGeneral-puropose I/O Analog-toAnalog-to-Digital Converter Brown Out Reset Comparator A, A+ Digital-toDigital-to-Analog Converter Timers Direct Memory Access Controller ESP430 ESP430 (integrated in FE42xx devices) FE42xx LCD/LCD_A/LCD_B Op Amps Hardware multiplier 16-05-2013 Mahesh J. vadhavaniya 84
  • 16-05-2013 Mahesh J. vadhavaniya 85
  • AVR Microcontroller Family 16-05-2013 Mahesh J. vadhavaniya 86
  • AVR General Features Enhanced RISC architecture with mostly fixed-length fixedinstruction, load-store memory access and 32 generalloadgeneralpurpose registers. registers. A two-stage instruction pipeline that speeds up execution. twoexecution. Majority of instructions take one clock cycle. cycle. Up to 10-MHz clock operation. 10operation. Wide variety of on-chip peripherals, including digital I/O, onperipherals, ADC, EEPROM, Timer, UART, RTC timer, PWM etc. etc. Internal program and data memory. memory. 16-05-2013 Mahesh J. vadhavaniya 87
  • AVR General Features In-System programmable (ISP). InISP) Available in 8-pin to 64-pin size to suit wide variety of 64applications. applications. Up to 12 times performance speedup over conventional CISC controllers. controllers. Wide operating voltage from 2.7 V to 6.0 V. Simple architecture offers a small learning curve to the uninitiated. uninitiated. 16-05-2013 Mahesh J. vadhavaniya 88
  • What does AVR RISC mean ? The acronym AVR has been reported to stand for: for: Advanced Virtual RISC and also for the chip's designers: designers: AlfAlf-Egil Bogen and Vegard Wollan who designed the basic architecture at the Norwegian Institute of Technology. Technology. RISC stands for Reduced Instruction Set Computer. Computer. CPU design with a reduced instruction set as well as a simpler set of instructions (like for example PIC and AVR) 16-05-2013 Mahesh J. vadhavaniya 89
  • Manufacturers Intel, Freescale, Microchip (PIC), TI, Zilog. Freescale, Zilog. Atmel AVR : Many Types, tinyAT, megaAT, automotive tinyAT, megaAT, Lighting, LCD Share unified platform Different #s of I/O control Built- PullBuilt-in Pull-up resistors Ethernet, Serial Data, Auxiliary Power, USB Analog I/O, Packaging, Interrupts, Math, JTAG Get the right amount of memory for the job 16-05-2013 Mahesh J. vadhavaniya 90
  • AVR Growing Family Tiny AVR family 8 – 32 pin general purpose microcontrollers. microcontrollers. 16 family members. members. MEGA AVR family 32 100 pin microcontrollers. microcontrollers. 23 family members. members. general purpose ASSP AVRs USB, CAN and LCD Motor Control and Lighting Automotive Battery Management 8 family members. members. 16-05-2013 Mahesh J. vadhavaniya 91
  • AVR Architecture 16-05-2013 Mahesh J. vadhavaniya 92
  • AVR – A Single Chip Solution 16-05-2013 Mahesh J. vadhavaniya 93
  • AVR – A Single Chip Solution 16-05-2013 Mahesh J. vadhavaniya 94
  • High – Level Integration 16-05-2013 Mahesh J. vadhavaniya 95
  • AVR Mega 8 Features 8-Kbyte self-programming selfFlash Program Memory 1-Kbyte SRAM 512 Byte EEPROM 6 or 8 Channel 10-bit A/D10A/Dconverter. converter. Up to 16 MIPS throughput at 16 Mhz. Mhz. 2.7 - 5.5 Volt operation. operation. 16-05-2013 Mahesh J. vadhavaniya 96
  • AT Mega 8 Pinout 16-05-2013 Mahesh J. vadhavaniya 97
  • ATMega 16 Features 131 Instructions 32 8-bit GP registers Throughput up to 16 MIPS 16K programmable flash (instructions) 16K 512Bytes 512Bytes EEPROM 1K internal SRAM Timers, serial and parallel I/O, ADC 16-05-2013 Mahesh J. vadhavaniya 98
  • AVR CPU PC : address of next instruction IR: pre-fetched preinstruction ID: current instruction GPR: R0-R31 R0ALU 16-05-2013 Mahesh J. vadhavaniya 99
  • AVR Memory Flash: Machine instructions go here SRAM: For runtime data Note bus independence for data and instructions EEPROM: Secondary storage EEPROM and Flash memories have a limited lifetime of erase/write cycles 16-05-2013 Mahesh J. vadhavaniya 100
  • Flash Memory Programs reside in word addressable flash storage Word addresses range from 0000-1FFF (PC is 13 0000bits) Byte addresses range 0000-3FFF (0x4000=16K) 0000Harvard Architecture It is possible to use this storage area for constant data as well as instructions, violating the true spirit of this architecture Instructions are 16 or 32-bits 32Most are 16-bits and are executed in a single clock 16cycle 16-05-2013 Mahesh J. vadhavaniya 101
  • SRAM The ATMega16 has 1K (1024 bytes) of byte addressable static RAM This is used for variable storage and stack space during execution SRAM addresses start at $0060 and go through $045F • The reason for not starting at zero will be covered later 16-05-2013 Mahesh J. vadhavaniya 102
  • Clock All processors are pushed through their fetch execute cycle by an alternating 0-1 signal, called a clock The ATMega16 can use an internal or external clock ATMega16 signal Clock signals are usually generated by an RC oscillator or a crystal • The internal clock is an RC oscillator programmable to 1, 2, 4, or 8 MHz • An external clock signal (crystal controlled) can be more precise for time critical applications 16-05-2013 Mahesh J. vadhavaniya 103
  • AVR Machine Language AVR instructions are 16 or 32-bits. 32Each instruction contains an opcode. opcode. Opcodes generally are located in the initial bits of an instruction. Some instructions have operands encoded in the remaining bits. Opcode and operands are numbers, but their containers are simply some of the bits in the instruction. 16-05-2013 Mahesh J. vadhavaniya 104
  • AVR 8 – bit RISC High Performance True single cycle execution Single-clock-cycle-perSingle-clock-cycle-per-instruction execution One MIPS (mega instructions per second) per MHz Up to 20 MHz clock 32 general purpose registers provide flexibility and performance when using high level languages prevents access to RAM Harvard architecture separate bus for program and data memory 16-05-2013 Mahesh J. vadhavaniya 105
  • AVR 8 – bit RISC Low Power Consumption 1.8 to 5.5V operation will use all the energy stored in your batteries A variety of sleep modes AVR Flash microcontrollers have up to six different sleep modes fast wake-up from sleep modes wakeSoftware controlled frequency 16-05-2013 Mahesh J. vadhavaniya 106
  • AVR 8 – bit RISC Compatibility AVR® Flash microcontrollers share a single core architecture use the same code for all families 1 Kbytes to 256 Kbytes of code 8 to 100 pins all devices have Internal oscillators 16-05-2013 Mahesh J. vadhavaniya 107
  • AVR 8 – bit RISC pico Power Technology “Pico Power enables AVR to achieve the industry’s lowest power consumption with 650 nA with a RTC (real time clock) running and 100nA in Power Down sleep” 100nA True 1.8V Supply Voltage Minimized Leakage Current Ultra Low Power 32 kHz Crystal Oscillator Digital Input Disable Registers Power Reduction Register 16-05-2013 Mahesh J. vadhavaniya 108
  • Code Size and Execution Time MSP430 and AVR are running a close race. But max speed on MSP430 is only 8 MHz. The C51 would have to run at 296 MHz to match the 16 MHz AVR. PIC 18 seems fast but requires 3 times as much code space. 16-05-2013 Mahesh J. vadhavaniya 109
  • Comparison of Code Size 16-05-2013 Mahesh J. vadhavaniya 110
  • Real Life Applications Complete Navigation Application. Application. C bitfields. bitfields. Car Radio Control. Control. DES Encryption / Decryption. Decryption. Three different modules from analog telephones. telephones. Reed – Solomon (error correction) encoder / decoder. decoder. Pager Protocol. Protocol. Refrigerator Control. Control. Battery Charger. Charger. Embedded Web Server. Server. Label / Recite printer. printer. 16-05-2013 Mahesh J. vadhavaniya 111