Dynamic Shift Frequency Scaling of ATPG Patterns <ul><ul><li>Aditya Ramachandran </li></ul></ul><ul><ul><li>Open-Silicon R...
Agenda <ul><li>Introduction </li></ul><ul><li>Scan Shift Power Analysis </li></ul><ul><li>Optimal Shift Frequency Calculat...
<ul><li>Test time  directly  affects cost-per-part </li></ul><ul><li>TEST TIME  TEST COST  COST-PER-PART </li></ul><ul><li...
Background Test Time Reduction <ul><li>Reduction of Test Time </li></ul>ATPG Test Time  ≈   ( # of Patterns x Length ) / F...
<ul><li>Factors Affecting Shift Frequency </li></ul>TIMING POWER Scan Shift Setup Timing Last Shift Launch Methodologies D...
Background Solution <ul><li>Power Dissipation is limiting Shift Frequency </li></ul><ul><li>Lower Power Dissipation  Highe...
Background Sample Power Analysis <ul><li>Results of Shift Power Analysis for Test Design   </li></ul>Leakage Dynamic
Background Solution <ul><li>Power Dissipation is limiting Shift Frequency </li></ul><ul><li>Lower Power Dissipation  Highe...
Scan Shift Power Analysis Flow <ul><li>Power Analysis Flow </li></ul>Simulation Create Saif Power Analysis Testbench Netli...
Optimal Shift Frequencies Step #1 <ul><li>STEP #1:  Calculate Frequency Bounds </li></ul>SHIFT POWER  <= FUNCTIONAL POWER ...
Optimal Shift Frequencies Step #1 Results <ul><li>STEP #1:  Calculate Frequency Bounds (Test Design) </li></ul>SHIFT POWER...
Optimal Shift Frequencies Step #2 <ul><li>STEP #2:  Choose a Set of Shift Frequencies </li></ul>Fmin <= {F1, F2.., Fn} <= ...
Optimal Shift Frequencies Step #3 <ul><li>STEP #3:  Assign New Shift Frequency to Patterns </li></ul>Foreach Pattern: Assi...
Optimal Shift Frequencies Step #3 Results <ul><li>STEP #3:  Assign New Shift Frequency to Patterns </li></ul>Shift Frequen...
Generation of Patterns <ul><li>Objectives </li></ul><ul><ul><li>Shift at multiple frequencies </li></ul></ul><ul><ul><li>A...
Creation of STIL File <ul><li>Create STIL File </li></ul><ul><ul><li>WaveformTables for each Shift Frequency </li></ul></u...
Generation of WGL <ul><li>In Tetramax </li></ul><ul><ul><li>Set DRC File to new STIL File </li></ul></ul><ul><ul><li>Read ...
Generation of WGL Example {  pattern 1 parallel_clock basic_scan  } {  load_unload  } vector(&quot;_default_WFT_&quot;) :=...
Verilog Testbench <ul><li>Write verilog testbench at highest shift frequency </li></ul><ul><ul><li>Hold is frequency-indep...
Generation of SDC <ul><li>Write SDC at highest shift frequency </li></ul><ul><ul><li>Hold is frequency-independent </li></...
Results and Analysis Test Design Information <ul><li>Test Design Parameters </li></ul><ul><ul><li>Max Scan Length : 4892 <...
Results and Analysis Effective Shift Frequency <ul><li>Effective Shift Frequency </li></ul>TOTAL PATTERNS  701 28MHZ  8 37...
Reduction in Test Time Original Patterns @ 28MHZ Scaled Patterns @ 53MHZ Max scan length = 4892 Number of patterns = 701 S...
Reduction in Test Cost Original Patterns @ 28MHZ Scaled Patterns @ 53MHZ Test Time  =~ 0.12 sec Test cost/sec = $0.0076 Sh...
Post-scaling Power Analysis
Advantages LOWER TEST TIME NO DESIGN CHANGES SCAN ARCHITECTURE INDEPENDENT POST-TAPEOUT/PRE-TAPEOUT
Conclusion <ul><li>What? </li></ul><ul><li>Why? </li></ul><ul><li>How? </li></ul>Multiple Shift Frequencies  for ATPG patt...
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Dynamic Shift Frequency Scaling Of ATPG Patterns

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Transcript of "Dynamic Shift Frequency Scaling Of ATPG Patterns"

  1. 1. Dynamic Shift Frequency Scaling of ATPG Patterns <ul><ul><li>Aditya Ramachandran </li></ul></ul><ul><ul><li>Open-Silicon Research Pvt.Ltd </li></ul></ul>
  2. 2. Agenda <ul><li>Introduction </li></ul><ul><li>Scan Shift Power Analysis </li></ul><ul><li>Optimal Shift Frequency Calculation </li></ul><ul><li>Generation of Scaled Patterns </li></ul><ul><li>Results and Analysis </li></ul><ul><li>Conclusion </li></ul>
  3. 3. <ul><li>Test time directly affects cost-per-part </li></ul><ul><li>TEST TIME TEST COST COST-PER-PART </li></ul><ul><li>UDSM Pattern count explosion </li></ul><ul><li>Test time reduction is required now more than ever ! </li></ul>Introduction 130NM and above 90NM and below Stuck-at Transition Path-Delay Bridging Stuck-at
  4. 4. Background Test Time Reduction <ul><li>Reduction of Test Time </li></ul>ATPG Test Time ≈ ( # of Patterns x Length ) / Frequency Pattern Compression Adaptive Scan More Scan Chains Increase!
  5. 5. <ul><li>Factors Affecting Shift Frequency </li></ul>TIMING POWER Scan Shift Setup Timing Last Shift Launch Methodologies Dynamic Power Dissipation! Power ~ Switching Activity Power ~ Frequency Increased Switching -> Lower Frequency Background Shift Frequency
  6. 6. Background Solution <ul><li>Power Dissipation is limiting Shift Frequency </li></ul><ul><li>Lower Power Dissipation Higher Shift Frequency </li></ul><ul><li>Assertion #1 : Power Dissipation is pattern-dependent </li></ul><ul><li>Assertion #2 : The difference is significant </li></ul>
  7. 7. Background Sample Power Analysis <ul><li>Results of Shift Power Analysis for Test Design </li></ul>Leakage Dynamic
  8. 8. Background Solution <ul><li>Power Dissipation is limiting Shift Frequency </li></ul><ul><li>Lower Power Dissipation Higher Shift Frequency </li></ul><ul><li>Assertion #1 : Power Dissipation is pattern-dependent </li></ul><ul><li>Assertion #2 : The difference is significant </li></ul>Solution Speed up low-power patterns
  9. 9. Scan Shift Power Analysis Flow <ul><li>Power Analysis Flow </li></ul>Simulation Create Saif Power Analysis Testbench Netlist VCD Saif Libraries - Synopsys VCS - Serial Patterns - vcd2saif - Per-Pattern saif - PrimePower - Saif-based flow
  10. 10. Optimal Shift Frequencies Step #1 <ul><li>STEP #1: Calculate Frequency Bounds </li></ul>SHIFT POWER <= FUNCTIONAL POWER Pdyn(new) + Plek <= Pfunc Pdyn(new) <= Pfunc - Plek Pdyn(old) * Fshift(new) <= (Pfunc – Plek) --------------------------------- Fshift(old) Max Power Minimum Shift Frequency Min Power Maximum Shift Frequency
  11. 11. Optimal Shift Frequencies Step #1 Results <ul><li>STEP #1: Calculate Frequency Bounds (Test Design) </li></ul>SHIFT POWER <= FUNCTIONAL POWER 0.01102W * Fmin <= ( 0.032W – 8.3e-4W ) ---------------------- 10MHZ 0.0048W * Fmax <= (0.032W – 8.3e-4W) ---------------------- 10MHZ Fmin = 28MHZ Fmax = 65MHZ
  12. 12. Optimal Shift Frequencies Step #2 <ul><li>STEP #2: Choose a Set of Shift Frequencies </li></ul>Fmin <= {F1, F2.., Fn} <= Fmax Reduces Complexity! For The Test Design: {28MHZ, 37MHZ, 52MHZ, 63MHZ} {35ns, 27ns, 19ns, 16ns}
  13. 13. Optimal Shift Frequencies Step #3 <ul><li>STEP #3: Assign New Shift Frequency to Patterns </li></ul>Foreach Pattern: Assign Maximum Fi from {F1,F2,..Fn} such that: Pshift(Fi) <= Pfunc
  14. 14. Optimal Shift Frequencies Step #3 Results <ul><li>STEP #3: Assign New Shift Frequency to Patterns </li></ul>Shift Frequency Allocation (Test Design) TOTAL PATTERNS 701 28MHZ 8 37MHZ 54 52MHZ 477 63MHZ 159
  15. 15. Generation of Patterns <ul><li>Objectives </li></ul><ul><ul><li>Shift at multiple frequencies </li></ul></ul><ul><ul><li>All else remain unchanged </li></ul></ul>
  16. 16. Creation of STIL File <ul><li>Create STIL File </li></ul><ul><ul><li>WaveformTables for each Shift Frequency </li></ul></ul><ul><ul><li>Use slowest shift table as Shift{} Waveform </li></ul></ul>load_unload&quot; { W &quot;_default_WFT_&quot;; C { ... } Shift { V { &quot;_clk&quot; = ...; &quot;_si&quot; = #; &quot;_so&quot; = #; } } ... } load_unload&quot; { W &quot;_default_WFT_&quot;; C { ... } Shift { W &quot;_SlowShift_WFT_&quot;; V { &quot;_clk&quot; = ...; &quot;_si&quot; = #; &quot;_so&quot; = #; } } ... }
  17. 17. Generation of WGL <ul><li>In Tetramax </li></ul><ul><ul><li>Set DRC File to new STIL File </li></ul></ul><ul><ul><li>Read in patterns in binary format </li></ul></ul><ul><ul><li>Write out patterns in WGL format </li></ul></ul><ul><li>Customize (perl script) </li></ul><ul><ul><li>Change timeplates for the shift task of each pattern </li></ul></ul>
  18. 18. Generation of WGL Example { pattern 1 parallel_clock basic_scan } { load_unload } vector(&quot;_default_WFT_&quot;) := [ 1 0 0.... ]; scan(&quot;_SlowShift_WFT_&quot;) := [ 1 1 0.... ], ..... { pattern 1 parallel_clock basic_scan } { load_unload } vector(&quot;_default_WFT_&quot;) := [ 1 0 0.... ]; scan(&quot;_Shift17ns_WFT_&quot;) := [ 1 1 0.... ], ..... Change timeplate for scan()
  19. 19. Verilog Testbench <ul><li>Write verilog testbench at highest shift frequency </li></ul><ul><ul><li>Hold is frequency-independent </li></ul></ul><ul><ul><li>Setup met at highest shift will meet at lower frequencies </li></ul></ul><ul><li>In STIL File </li></ul><ul><ul><li>Set Shift Waveform to fastest shift </li></ul></ul><ul><li>In Tetramax </li></ul><ul><ul><li>Set DRC File to new STIL File </li></ul></ul><ul><ul><li>Read in patterns in binary format </li></ul></ul><ul><ul><li>Write out verilog testbench for verification </li></ul></ul>
  20. 20. Generation of SDC <ul><li>Write SDC at highest shift frequency </li></ul><ul><ul><li>Hold is frequency-independent </li></ul></ul><ul><ul><li>Setup met at highest shift will meet at lower frequencies </li></ul></ul><ul><li>In STIL File </li></ul><ul><ul><li>Set Shift Waveform to fastest shift </li></ul></ul><ul><li>In Tetramax </li></ul><ul><ul><li>Set DRC File to new STIL File </li></ul></ul><ul><ul><li>Write SDC using write_timing_constraints </li></ul></ul>
  21. 21. Results and Analysis Test Design Information <ul><li>Test Design Parameters </li></ul><ul><ul><li>Max Scan Length : 4892 </li></ul></ul><ul><ul><li>Fault Model : Stuck-at </li></ul></ul><ul><ul><li>Number of Patterns : 701 </li></ul></ul>
  22. 22. Results and Analysis Effective Shift Frequency <ul><li>Effective Shift Frequency </li></ul>TOTAL PATTERNS 701 28MHZ 8 37MHZ 54 52MHZ 477 63MHZ 159 Effective Shift Frequency = 53MHZ
  23. 23. Reduction in Test Time Original Patterns @ 28MHZ Scaled Patterns @ 53MHZ Max scan length = 4892 Number of patterns = 701 Shift Period = 35ns Test Time =~ 0.12 sec Max scan length = 4892 Number of patterns = 701 Shift Period = 19ns Test Time =~ 0.06 sec Test Time is reduced by ~45%
  24. 24. Reduction in Test Cost Original Patterns @ 28MHZ Scaled Patterns @ 53MHZ Test Time =~ 0.12 sec Test cost/sec = $0.0076 Shipping Volume = 10Million Total Cost = $91219 Test Time =~ 0.06 sec Test cost/sec = $0.0076 Shipping Volume = 10Million Total Cost = $49597 Save $41,000 per 10M parts
  25. 25. Post-scaling Power Analysis
  26. 26. Advantages LOWER TEST TIME NO DESIGN CHANGES SCAN ARCHITECTURE INDEPENDENT POST-TAPEOUT/PRE-TAPEOUT
  27. 27. Conclusion <ul><li>What? </li></ul><ul><li>Why? </li></ul><ul><li>How? </li></ul>Multiple Shift Frequencies for ATPG patterns within the same pattern set To Reduce Test Time without excessive power dissipation Increase Shift Frequency of Patterns with Low Power Dissipation

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