Upcoming SlideShare
Loading in …5
×

Digital Circuit Verification Hardware Descriptive Language Verilog

2,333 views
1,575 views

Published on

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers.

A brief history

Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.

Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success...

Published in: Engineering
0 Comments
0 Likes
Statistics
Notes
• Full Name
Comment goes here.

Are you sure you want to Yes No
Your message goes here
• Be the first to comment

• Be the first to like this

No Downloads
Views
Total views
2,333
On SlideShare
0
From Embeds
0
Number of Embeds
5
Actions
Shares
0
Downloads
25
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Digital Circuit Verification Hardware Descriptive Language Verilog

1. 1. Digital System Design Digital Circuit Verification Hardware Descriptive Language Verilog
2. 2. Overview  More Structural Verilog Examples  Dataflow Modeling  Dataflow Verilog Examples  Writing Test Bench
3. 3. 4-1 Multiplexer - Structural Verilog Description module multiplexer_4_to_1_st_v(S, I, Y); input [1:0] S; // S is a vector with components S[1] and S[0] input [3:0] I; // I is a 4-bit input; vectors: I[0]…I[3] output Y; wire [1:0] not_S; // connecting NOT-AND wire [0:3] D, N; // D connecting AND-AND not // N  AND outputs gn0(not_S[0], S[0]), // gn0(output, input) gn1(not_S[1], S[1]); and g0(D[0], not_S[1], not_S[0]), g1(D[1], not_S[1], S[0]), g2(D[2], S[1], not_S[0]), g3(D[3], S[1], S[0]), g4(N[0], D[0], I[0]), g5(N[1], D[1], I[1]), g6(N[2], D[2], I[2]), g7(N[3], D[3], I[3]); or go(Y, N[0], N[1], N[2], N[3]); endmodule D0 g0 not_S[0]S[0] g4 N[0]
4. 4. 2-to-4 Line Decoder Structural Verilog // 2-to-4 Line Decoder: Structural Verilog Description. // (See Figure 4-10 for logic diagram) module decoder_2_to_4_st_v(EN, A0, A1, D0, D1, D2, D3); input EN, A0, A1; output D0, D1, D2, D3; wire A0_n, A1_n, N0, N1, N2, N3; not go(A0_n, A0), g1(A1_n, A1); and g3(N0, A0_n, A1_n), g4(N1, A0, A1_n), g5(N2, A0_n, A1), g6(N3, A0, A1), g7(D0, N0, EN), g8(D1, N1, EN), g9(D2, N2, EN), g10(D3, N3, EN); endmodule A1_n N0 N1 g3 A0_n g6 N3
5. 5. Dataflow Verilog Modeling  A dataflow description is based on function rather than structure.  A dataflow uses a number of operators that act on operands to produce the desired function  Boolean equations are used in place of logic schematics.
6. 6. 4-1 Multiplexer - Dataflow Verilog // 4-to-1 Line Multiplexer: Dataflow Verilog Description (Boolean) // (See Figure 4-14 for logic diagram) module multiplexer_4_to_1_df_v(S, I, Y); input [1:0] S; input [3:0] I; output Y; assign Y = (~ S[1] & ~ S[0] & I[0])| (~ S[1] & S[0] & I[1]) | (S[1] & ~ S[0] & I[2]) | (S[1] & S[0] & I[3]); endmodule
7. 7. 2-to-4 Line Decoder Dataflow Verilog // 2-to-4 Line Decoder with Enable: Dataflow Verilog Desc. // (See Figure 4-10 for logic diagram) module decoder_2_to_4_df_v(EN, A0, A1, D0, D1, D2, D3); input EN, A0, A1; output D0, D1, D2, D3; assign D0 =(EN & ~A1 & ~A0); assign D1 =(EN & ~A1 & A0); assign D2 =(EN & A1 & ~A0); assign D3 =(EN & A1 & A0); endmodule
8. 8. Writing a Test Bench  A test bench in an HDL program for applying stimulus to an HDL design in order to test it and observe the response during simulation. initial begin A = 0; B = 0; // @ t = 0 A and B are set to 0 #10 A = 1; // 10 time units later, A is changed to 1 #20 A = 0; B = 1; // @ t = 30 A is changed to 0 and B to 1 end
9. 9. Test Bench Example //HDL Example //------------------------------------------ //Gate-level description of a combinational circuit module analysis (A,B,C,F1,F2); input A,B,C; output F1,F2; wire T1,T2,T3,F2not,E1,E2,E3; or g1 (T1,A,B,C); and g2 (T2,A,B,C); and g3 (E1,A,B); and g4 (E2,A,C); and g5 (E3,B,C); or g6 (F2,E1,E2,E3); not g7 (F2not,F2); and g8 (T3,T1,F2not); or g9 (F1,T2,T3); endmodule
10. 10. //Stimulus to analyze the circuit module test_circuit; reg [2:0]D; wire F1,F2; analysis circuit(D[2],D[1],D[0],F1,F2); initial begin D = 3'b000; repeat (7) #10 D = D + 1'b1; end initial \$monitor ("ABC = %b F1 = %b F2 =%b ",D, F1, F2); endmodule Test Bench Example (continued)