A designer may use any technology to implement a design – normally the decision is dictated by economic factors
Rather than try to draw any hard-and-fast comparisons between the costs of different implementation techniques, it is more instructive to examine here the relationship between the 'start-up' and 'high-volume' costs of the different techniques, when a family of curves of the form given below may be constructed, showing that the most economic form of implementation depends upon the volume of devices to be used.
Note that for any given volume, one technology will offer the lowest cost… For successive choices, the silicon utilisation is more efficient (and so unit costs are lower), but the initial cost in terms of design time, CAD facilities and manufacturing are higher.
Standard = ‘fixed function’ What’s the difference between ‘standard’ and ‘custom’ components? (If you sell enough custom chips they become standard…) ‘ Custom’ relates to the layout procedure ‘ Semicustom’ technologies allow the economies of mass production with the ability to customise a device for a specific application. Also known as ‘ASICs’.
EET 3350 Digital Systems Design Textbook: John Wakerly Chapter 9: 9-5 CPLDs 1
CPLDs• Overview of FPLDs – History – Tradeoffs• CPLDs – General Description – Basic Architecture• Specific Vendor Devices – Xilinx – Altera• Xilinx XC9500 Series• CPLD Problems 2
Hierarchy of Logic Implementations Logic Standard ASIC Logictoday’s focus Programmable Logic Devices Gate Cell-Based Full Custom (FPLDs) Arrays ICs ICs SPLDs CPLDs (e.g., PALs) FPGAs Acronyms Common Resources SPLD = Simple Programmable Logic Device Configurable Logic Blocks (CLB) PAL = Programmable Array Logic – Memory Look-Up Table (LUT) CPLD = Complex PLD – AND-OR planes – Simple gates FPGA = Field Programmable Gate Array Input / Output Blocks (IOB) ASIC = Application Specific IC – Bidirectional, latches, inverters, pullup/pulldowns Interconnect or Routing – Local, internal feedback, and global 3
Field-Programmable Logic Devices• Component function is defined by user under program control• Logic Cells are interconnected by programming• Advantages: – Flexible design that changes by reprogramming, ease of design changes – Reduce prototype-product time – Large scale integration (over 100,000 gates) – Reliability increased, low financial risk – Smaller device, low start-up cost 4
FPLD Capacities• “Equivalent gates” refers loosely to the number of two- input NAND gates.• The chart serves as a guide for selecting a device for an application according to the logic capacity needed.• Each type of FPLD is inherently better suited for some applications than for others. 5
Which Implementation Technology?• Economic versus technical factors – The next few slides off a comparison of economic and technical factors associated with these technologies standardcomponents CPLD Gate Std. Full SSI/MSI SPLD FPGA Array Cell Custom semicustom technologies 7
Comparison of Implementations• The table below offers a comparison of the major implementation technologies over four key factors Gate Standard Full SSI/MSI SPLD FPGA Array Cell Custom Gates/Component 5 - 100 50 - 5K 100 - 10K 500 - 100K 10K - 500K 100K - 10M Cost/Gate High Low NRE Cost ($) - 1-2K 2-10K 5-50K 10-100K 50K-5M Development time - 1-2 1-2 2-20 5-50 20-200 (weeks) 8
Comparison of Implementations Circuit Cost As A Function Of VolumeCost Discrete Full custom Volume 9
Evolution of Implementations• CPLDs and FPGAs continue to evolve in parallel ‘standard 1960 components’ SSI ‘semicustom components’ 1970 MSI Gate Array Simple PLD LSI Standard Cells 1980 VLSI CPLD FPGA 1990 2000 parallel development Today 10
Three FPLD Types• Simple Programmable Logic Device (SPLD) – LSI device – Less than 1000 logic gates• Complex Programmable Logic Device (CPLD) – VLSI device – Higher logic capacity than SPLDs• Field Programmable Gate Array (FPGA) – VLSI device – Higher logic capacity than CPLDs Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 11
Three FPLD Types• Simple Programmable Logic Device (SPLD) – PLA or PAL – Fixed internal routing, deterministic propagation delays• Complex Programmable Logic Device (CPLD) – Multiple SPLDs onto a single chip – Programmable interconnect• Field Programmable Gate Array (FPGA) – An array of logic blocks – Large number of gates, user selectable interconnection, delays depending on design and routing Programmable – A high ratio of flip-flops to logic resources Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 12
SPLDs• SPLDs = Simple PLDs• Popular SPLD Architecture Types – Programmable Logic Array, PLA – Programmable Array Logic, PAL (Vantis) – General Array Logic, GAL (Lattice) – others• Architecture Differences – AND versus OR implementation – Programmability (e.g., EE) – Fundamental logic block Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 13
SPLDs • We have already taken a close look at SPLDs • A PLA-like SPLD is illustrated at left – PAL and GAL devices offered a Logic Functions somewhat better solution • SPLDs are good alternative to Sums using SSI and MSI devices – Especially if re-programmable Programmable Logic Devices (FPLDs)Product Terms SPLDs CPLDs FPGAs (e.g., PALs) 14
SPLDs• Conventional programmable logic – PALs, PLAs, GALs – standard parts like GAL22V10 and PAL16R4 are available from multiple vendors• Includes programmable logic cells to a limited degree (programming options in I/O cells, may have fixed AND/OR gates for logic), limited routing network• Lowest density of all programmable devices, however, can offer very high performance• SPLDs have nearly replaced TTL logic which was the Programmable Logic Devices dominate approach to logic (FPLDs) implementation SPLDs CPLDs FPGAs (e.g., PALs) 15
How to Expand SPLD Architecture?• Increase number of inputs and outputs in a conventional PLD? – e.g., 16V8 → 20V8 → 22V10 – Why not → 32V16 → 128V64 ?• Problems: – n times the number of inputs and outputs requires n2 as much chip area – too costly – logic gets slower as number of inputs to AND array increases Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 16
How to Expand SPLD Architecture?• Solution: – Multiple SPLDs with a relatively small programmable interconnect – Less general than a single large PLD – Can use software “fitter” to partition into smaller PLD blocks Programmable Logic Devices (FPLDs) CPLD Architecture SPLDs CPLDs FPGAs (e.g., PALs) 17
CPLDs• PALs and GALs are available only in small sizes – equivalent to a few hundred logic gates• For bigger logic circuits, complex PLDs or CPLDs can be used.• CPLDs contain the equivalent of several PALs/GALs – linked by programmable interconnections – all in one integrated circuit (IC)• CPLDs can replace thousands, or even hundreds of thousands, of individual logic gates – increased integration density Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 18
Complex PLDs• Some CPLDs are programmed using a PAL programmer, but this method becomes inconvenient for devices with hundreds of pins.• A second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal computer.• The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function. Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 19
Complex PLDs• Each manufacturer has a proprietary name for its CPLD programming system• For example, Lattice calls it "in-system programming"• However, these proprietary systems are beginning to give way to a standard from the Joint Test Action Group (JTAG) Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 20
Complex PLDs versus FPGAs• Xilinx, for example:• Xilinx CPLD devices that are cheaper and have fewer gates than Xilinx FPGAs• Meant for interfacing rather than heavy computation• Built-in flash memory – Compare to FPGA which needs external configuration memory• Xess board has XC9572XL part – Approximately $2-$7 in quantities of one – vs. ~$15-20 for the Spartan2 FPGA on the board – Larger quantities much lower – 1600 gates, 72 registers Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 21
CPLD Architecture• Simplified CPLD architecture• Small number of largish PLDs (e.g., “36V18”) on a single chip• Programmable interconnect between PLDs• Large number of I/O blocks• Large number of pins 22
CPLD Architecture• Generalized architecture for a complex PLD• Programmable Interconnect Array – Capable of connecting any LAB input or output to any other LAB• Logic Array Blocks – Complex SPLD-like structure Programmable Logic Devices (FPLDs)• Input/Output Blocks SPLDs CPLDs FPGAs (e.g., PALs) 23
CPLD Architecture • Each of the SPLD-like blocks in a CPLD can be programmed as with a PAL or GAL • Many SPLD-like blocks (e.g., LABs) are included in one CPLDFeedback Outputs • LABs can be interconnected to build larger logic systems Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs CPLD Architecture (e.g., PALs) 24
CPLDs• Composition of Complex PLDs – typically composed of 2-64 SPLDs – interconnected using sophisticated logic – includes macrocells (more about these later) – includes input/output blocks• Economical for designing large systems• Fast – switching speed Programmable Logic Devices (FPLDs) SPLDs CPLDs FPGAs (e.g., PALs) 25
CPLDs• Complex PLDs have arrays of PLDs on one chip, with an interconnection matrix connecting them.• Timing performance can be more predictable than FPGAs because of simpler interconnect structure.• Density is normally less than most FPGAs (although high end CPLDs will have about the same density as low-end FPGAs).• Performance of CPLDs is usually better than FPGAs, but depends on vendor, number of cells in CPLD, and Programmable Logic Devices (FPLDs) compared FPGA. SPLDs CPLDs FPGAs (e.g., PALs) 26
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