Documentation Standards of an IC

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Documentation Standards of an IC

  1. 1. EET 3350 Digital Systems Design John Wakerly Chapter 5: Part 1 Documentation Standards 1
  2. 2. Documentation Standards• Good documentation is essential for correct design and efficient maintenance of digital systems• It should be accurate complete and instructive• One should be able to figure out how the system works just by reading the documentation• It depends on the system complexity and the engineering and manufacturing environment 2
  3. 3. Documentation StandardsA good documentation package should generally contain at least the following• Circuit specification• Block diagram• Schematic diagram• Timing diagram• Structured logic device description• Circuit description 3
  4. 4. Circuit specification• Describes exactly what the circuit or system is supposed to do• Includes description of all inputs and outputs and functions to be performed• It does not have to specify how the system achieves the result• It just specifies what the results are supposed to be• It is common practice to incorporate one or more of the documents below the specifications to describe how the system works 4
  5. 5. Block diagram• It is an informal pictorial representation of the system’s major functional modules and their basic interconnections Schematic diagram• It is a formal specification of the electrical components of the system, their interconnections, and all of the details of component inputs, outputs, and interconnections needed to construct the system• It includes IC types, reference designators and pin numbers, title blocks and names for all signals, page-to- page connectors• A schematic drawing program should have the ability to generate a bill of materials from the schematic 5
  6. 6. Timing diagram • It shows the values of various logic signals as a function of time, including the cause and effect delays between critical signals Structured logic device description• It describes the internal function of a programmable logic device (PLD), field programmable gate array (FPGA), or application specific integrated circuit (ASIC).• It is normally written in a hardware descriptive language (HDL) such as ABEL, VHDL or Verilog• It may also be put in the form of logic equations, state tables, or state diagrams• In some cases a conventional programming language such as C may be used to model the operation of a circuit to specify its behavior 6
  7. 7. Circuit description• It is a narrative text document that, in conjunction with the other documentation, explains how the circuit works internally• It lists all the assumptions which have been made• It also points out the potential pitfalls in the circuits design and operation• It describes any non-obvious tricks used in the design• It contains definitions of acronyms and other specialized terms and has references to related documentation 7
  8. 8. Block diagram• It shows the inputs, outputs, functional modules, internal data paths and important control signals of the system• It should not be too detailed• It usually occupies only one page• It shows the important block elements and how they work together• Large systems may require additional block diagrams of individual subsystems• There has to be a “top-level” block diagram showing the entire system• A sample block diagram is shown in the next slide 8
  9. 9. Block Diagram 9
  10. 10. Block diagram• Each block is labeled with the function of the block, not the individual chips that comprise it• A bus is a collection of two or more related signals and usually shown with a double or heavy line• A slash and number may indicate the how many lines are contained in the bus• Alternately the size may be denoted in the bus name as INBUS[31..0]• Active levels and inversion bubbles may not appear in the block diagram• All important control signals and buses should have names and the same names should appear in the detailed schematic• The flow of control and data should be clearly indicated• Inputs and outputs could be on any side of a block, and the direction of flow may be arbitrary• Arrowheads are used on buses and signals to remove ambiguity 10
  11. 11. Schematic diagrams• Details of component inputs, outputs, and interconnections• IC type (74HCT00 or 74LS00)• Reference designators (U for “unit”)• Pin numbers ( 1, 2, 3)• Names for all signals (A, B, X) 11
  12. 12. Example schematic 12
  13. 13. Schematic diagrams• Logic diagrams and schematics should be drawn with gates in their normal orientation with inputs on the left and outputs on the right• Logic symbols for larger scale logic elements are also drawn with inputs on the left and outputs on the right• A complete schematic should be drawn with system inputs on the left and outputs on the right and the general flow of signals should be from left to right• If an input or output appears at the middle of a page it should be appropriately extended to the left or right of the page• All signal paths on the page should be connected when possible; paths may be broken if the diagram gets crowded
  14. 14. Schematic diagrams• Schematics are best drawn with the page used in landscape format• Schematics that do not fit into 1 page are broken up into individual pages in a way that minimizes the connections (and confusion) between pages• Signal flags are used when signals travel from one page to the other• A multiple page schematic usually has a flat structure• In this each page is carved out from the complete schematic and can connect to any other page as if all the pages were on one large sheet as shown in the next slide
  15. 15. Flat schematic structure 15
  16. 16. Schematic diagrams• Schematics can also be constructed hierarchically, as shown in the next slide• In this approach, the “top-level” schematic is just one page that may take the place of a block diagram• Typically the “top-level” schematic contains no gates or other logic elements; it only shows blocks corresponding to major subsystems and their interconnections• The blocks or subsystems are in turn defined on lower-level pages, which may contain ordinary gate level descriptions, or which may themselves use blocks defined in lower level hierarchies• If a particular lower level hierarchy needs to be used more than once, it may be used multiple times by the higher level pages
  17. 17. Hierarchical schematic structure 17
  18. 18. Schematic diagrams• Most computer –aided logic design systems support both flat and hierarchical schematics• Proper signal naming is important in both styles• Signal names intended to connect with each other should have the same name• In hierarchical schematics, one should be very careful in naming the external interface signals on pages in the lower levels of hierarchy• These names will appear inside the blocks corresponding to these pages when they are used at the higher levels of hierarchy• Its very easy to transpose signal names or use the wrong active level leading to incorrect results• In many schematic programs signals appear to be connected but are not, or vice versa which could lead to errors
  19. 19. Other Documentation• Timing diagrams – Output from simulator – Specialized timing-diagram drawing tools• Circuit descriptions – Text (word processing) – Can be as big as a book (e.g., typical Cisco ASIC descriptions) – Typically incorporate other elements (block diagrams, timing diagrams, etc.) 19
  20. 20. Gate symbols 20
  21. 21. DeMorgan equivalent symbols Which symbol to use? Answer depends on signal names and active levels. 21
  22. 22. Signal names and active levels• Signal names are chosen to be descriptive.• Active levels -- HIGH or LOW – named condition or action occurs in either the HIGH or the LOW state, according to the active-level designation in the name. 22
  23. 23. Example HIGH when error occursLogic ERRORCircuit OK_L LOW when error occursLogic ERROR_L ERRORCircuit ERROR1_L 23
  24. 24. Signal name, logic expression and logic equation• A signal name is just a name – an alphanumerical label• A logic expression combines signal names using the operators of switching algebra – AND, OR, NOT, etc.• A logic equation is an assignment of a logic expression to a signal name – it describes one signal’s function in terms of other signals• ENABLE = TEST + (READY•REQUEST)
  25. 25. Active Levels for pins• When we draw the outline of an AND or OR symbol, or a rectangle representing a larger-scale logic element, we think of the given logic function as occurring inside that symbolic outline ENABLE ENABLE DO DO MY MY THING THING Same elements with active AND, OR AND a Large- low inputs and outputs scale Logic element
  26. 26. Active Levels for pins• The AND and OR gates have active high inputs- they require 1s on their inputs to assert their output• The large scale element has an active high ENABLE input, which must be 1 to enable the element to do its thing• In the diagrams on the right hand side exactly the same logic functions are performed inside the symbolic outlines, but the inversion bubbles indicate that 0s must now be applied to the input pins to activate the logic functions and the outputs are 0 when they are “doing their thing”• Thus active levels may be associated with the input and output pins of gates and large scale elements
  27. 27. Active Levels for pins• We use an inversion bubble to indicate an active low pin and the absence of a bubble to indicate active high pin Four ways of obtaining AND function• AND gate performs regular AND function• NAND gate also performs AND function but produces active-low output• NOR gate also performs AND function but accepts active-low inputs and produces active-high output• OR gate also performs AND function but accepts active-low inputs and produces active-low output
  28. 28. Active Levels for pins• All the four gates can be said to perform the same function: the output of each gate is asserted if both of its inputs are asserted• Similarly the OR function can be obtained using the same idea where the output of each gate is asserted if either of the inputs are asserted Four ways of obtaining OR function
  29. 29. Bubble to Bubble logic Design• It is the practice of choosing logic symbols and signal names, including active level designators, that make the function of a logic circuit easier to understand.• Usually this means choosing signal names and gate types and symbols so that most of the inversion bubbles cancel out and the logic diagram can be analyzed as if all of the signals were active high• GO = READY•REQUEST
  30. 30. Sequential-Circuit Documentation StandardsGeneral requirements• Basic documentation standards in areas like signal naming, logic symbols and schematic layout apply to digital systems as a whole• The following ideas are highlighted for systems that are particularly sequential• State-machine layout - Within a logic diagram, a collection of flip flops and combinational logic that forms a state machine should be drawn together in a logical format on the same page• Cascaded elements - Registers, counters and shift registers that use multiple ICs should have the ICs grouped together so that the cascading structure is obvious 30
  31. 31. Sequential-Circuit Documentation Standards• Flip-flops - the symbols for individual sequential circuit elements especially flip-flops should rigorously follow the appropriate drawing standards, so that the type function and clocking behavior of the elements are clear• State machine descriptions - State machines should be described by state tables, state diagrams, transition lists, or text files in a state machine description language such as ABEL, VHDL or Verilog 31
  32. 32. Sequential-Circuit Documentation Standards• Timing diagrams - The documentation package for sequential circuits should include timing diagrams that show the general timing assumptions and timing behavior of the circuit• Timing specifications - A sequential circuit should be accompanied by a specification of the timing requirement for proper internal operation (e.g. Maximum clock frequency), as well as the requirements for any externally supplied inputs (e.g. setup time, hold time, minimum pulse width etc..) 32
  33. 33. Sequential-Circuit Documentation StandardsLogic Symbols• Flip-flops are usually drawn as a rectangular shaped symbols and follow the same general guidelines as inputs to the left, outputs to the right, bubbles for active levels and so on. In addition some specific guidelines are as follows: - A dynamic indicator is placed on edge triggered clock inputs - A postponed–output indicator is placed on master/slave outputs that change at the end of the interval during which the clock is asserted - Asynchronous preset may be shown at the top and clear at the bottom of a flip-flop symbol 33
  34. 34. Sequential-Circuit Documentation StandardsState-Machine Descriptions• Various representations of state machines: - Word descriptions - State tables - State diagrams - Transition lists - VHDL programs• Having all these different ways to represent state machines is a problem – too much to learn! 34
  35. 35. Sequential-Circuit Documentation StandardsState-Machine Descriptions• Since we have already finished state machine designing we know that there are a lot of opportunities to mess up if one translates the state diagram into a state table into a transition table into excitation equations, output equations and finally into a logic diagram• The best solution is to write state-machine programs directly in VHDL and avoid alternate representations other than general summary word descriptions 35
  36. 36. Sequential-Circuit Documentation StandardsTiming Diagrams• Timing diagram illustrates the logical behavior of signals in a digital circuit• They are used both to explain the timing relationships among signals within a system and to define the timing requirements of external signals that are applied to the system• Signal transitions are drawn as slanted lines just to remind that they do not occur in zero time in real circuits• Arrows are drawn to show causality – which input transitions cause which output transitions 36
  37. 37. Sequential-Circuit Documentation StandardsTiming Diagrams• The most important information provided by a timing diagram is a specification of the delay between transitions• Delays could vary when the output changes from LOW to HIGH and when it changes from HIGH to LOW• Delay in real circuits is usually measured between the centre points of transitions 37
  38. 38. Sequential-Circuit Documentation StandardsTiming Specifications• Timing diagram is usually accompanied by timing table that specifies each delay amount and the conditions under which it applies• A timing table may specify a range of values given by minimum, typical and maximum values for each delay - minimum: This is the smallest delay that a path will ever take, most well designed circuits do not depend on this number; that is they will work properly even if the delay is zero 38
  39. 39. Sequential-Circuit Documentation StandardsTiming Specifications - typical: It is the delay corresponding to the operation of the device under near-ideal conditions - maximum: This specification is the one that is most often used by experienced designers since a path never has a delay longer than the maximum. It is over the full operating range of voltage and temperature, sort of worst case conditions 39
  40. 40. Sequential-Circuit Documentation StandardsTiming Margin• It indicates how much “ worse than worst-case” the individual components of a circuit can be without causing the circuit to fail• Well designed circuits have timing margins to allow for unexpected circumstances• Setup-time margin: It is given by tclk – tffpd – tcomb – tsetup The maximum propagation delays are used to calculate it• Hold-time margin: It is given by tffpd(min) + tcomb(min) – thold. The minimum propagation delays are used to calculate it 40
  41. 41. Debouncer• Bouncing – Behavior of mechanical of switches which causes their contacts to close, and open several times before finally reaching a resting or stable closed state.• Typically switches bounce for 10 – 20 ms, which is a very long time compared to the switching speeds of logic gates.
  42. 42. • Debouncing – providing a single signal change or pulse for each switch transition.
  43. 43. Push First Contact BounceSWU_LSWD_LDSW_LDSW

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