VLSI DESIGN PRESENTATION DSP IMPLEMENTATION THROUGH FPGA
Reconfigurable Computing for Digital Signal Processing
Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade.While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications,increasingly new system implementations based on reconfigurble computing is being considered.
Compared to ASIC or FPGA hardware solutions a DSP chip is by far the slowest option.
DSPs just draw too much power for portable applications.
Power down sides of DSP chips become of too much of a deterrent ,most designers have turned to ASIC hardware solutions.A hard-wired , cell based custom chip.An ASIC solution will be faster , more efficient , and cheaper than its DSP chip alternative.
Many characteristics of FPGA devices,in particular,make them especially attractive for use in digital signal processing systems.The fine-grained parallelism found in these devices is well matched to the high sample rates and distributed computation often required of signal processing applications in areas such as image audio,and speech processing.Given the highly pipelined and parallel nature of many DSP tasks,such as image and speech processing,these implementations have exhibited substantially better performance than standard PDSPs
A Reconfigurable architecture which incorporates a reconfigurable coprocessor into a DSP can have performance benefits for a reasonable increase in chip area.In addition,DSPs have many architectural features which make a combination with reconfiguarble logic feasible and beneficial.Despite the raw clock rate disadvantage of DSPs when compared with general purpose microprocessors,DSPs serve an important role in high-performance,embedded computing;A reconfigure processor on-chip can help DSPs exploit more of the parallelism found in digital signal processing applications,thus improving the processor’s overall performance
Designers creating an FPGA implementation begin with the knowledge that the multipliers they will need are often already fabricated on the chip.Whereas DSP processors typically have only 8 dedicated multipliers at their disposal,a higher –end FPGA device such as Altera’s Stratix offers up to 224 dedicated multipliers plus additional logic element-based multipliers are needed.
Designing Digital Signal Processing with FPGAs
Complex digital signal processing applications such as finite impulse response (FIR) filters,modulation-demodulation , and encryption call for larger multiplier requirements.Given the number of multipliers available with an FPGA ,the designer’s job of defining an architecture for these types of digital signal processing applications tends to be quick and extremely flexible.Higher- end FPGA devices often feature multiple DSP blocks that can provide data throughput of up to 56 GMACS.
Once a system designer has arrived at an architecture that runs the algorithm efficiently , she or he typically turns the job over to a team of hard ware designers.This team,in turn, translates the architecture into a register transfer level description in HDL (VHDL or Verilog).This translation allows hardware designers to consider the design at the appropriate level of abstraction.And it is here that a major advantage of FPGA over ASIC can be found.
During the Place & Route phase of FPGA design,all logic components are located,wiring connections are made,and a final timing analysis is performed.Place and route software,such as Altera’s Quartus II uses the hardware designer’s timing constraints to create optimal logic mapping and placement.Critical timing paths are optimized first to help achieve timing closure faster and deliver faster performance.
FPGA that has been optimized to perform a digital signal processing task,will run anywhere from 10 times to more than 1000 times faster than a single DSP chip.Whereas a DSP processor typically employs serial processing,the parallel capacities inherent FPGA architecture will always give them both a significant edge over DSPs.DSPs just draw too much power for portable applications like Cellular Mobile Communications and Wireless LAN.Texas Instrument doesn’t use DSP for WLAN.
An increasing number of designers are turning to programmable logic devices,or FPGA , as a way to navigate the software-hardware extremes of DSP or ASIC design solutions.An FPGA that’s been enhanced for digital signal processing gives you unlimited customizing options in a chip without all the silicon physical-design work required for an ASIC solution.
Key tasks to the rise of FPGA in the signal Processing realm could be assigned to hardware to take advantage of optimum speed , power consumption , and per unit costs,while other tasks are performed by software to speed time to market and ease legacy compatibility.With digital signal processing continuing to be a critical component in the evolution of wireless networks and in multimedia .FPGA will grow in their ability to deliver state-of-art signal processing in a fraction of the time than ASIC.
Implementing DSP Designs in Altera Stratix Devices
The most commonly used DSP functions are FIR (Finite Impulse response)filters,IIR(Infinite Impulse response filters,FFT(Fast Fourier Transform),DCT (direct Cosine Transform),Encoder/Decoder and Error Correction/Detection functions.All of these blocks perform intensive arithmetic operations such as add,subtract,multiply,multiply-add or multiply-accumulate.
A refinement of the programming methodology for the DSP hybrid processor as well as the many issues of interfacing the RL with the DSP.The intention is to make the programming task resemble more of a software creation problem than a hardware design exercise,a requirement crucial in making the architecture usable by DSP programmers and not just hardware designers. Future work will also quantify the effects of frequent reconfiguration on application performance.
Thank You By: Abhijay Singh Sisodia 0905EC051002