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This presentation is about the emerging and future possible trends of the exciting field of nanotechnology. Scientists and engineers are working on a smaller scale day-by-day to increase portability ...

This presentation is about the emerging and future possible trends of the exciting field of nanotechnology. Scientists and engineers are working on a smaller scale day-by-day to increase portability and smaller devices, and to change the way we see the world and live in!

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Nano-electronics Nano-electronics Presentation Transcript

  • NANO-ELECTRONICS Abhishek Syal BITS, Pilani
  • Devices
    • Nanotweezers .. Harvard
    • Nanomechanical Resonator .. 500 MHz, Q= 2,50,000
    • Memory Elements: molecular memories, gates, switches
    • Nanowire Sensors
    • SETs, RTDs
  • Introduction
    • Early Stages of Development – conceptual
    • Natural nanosized machines—
    • flagellar motor of bacteria, driven by ATP
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  • Challenges
    • Smaller dimensions-increased sensitivity to fluctuations
    • Manufacturability and reproducibility
  • What is Nanotechnology in Elec?
    • Switching devices of nanometer (below 100nm, typically 10nm) dimensions define nanotechnology.
    Logic (Our Focus) Memory Fabrication Nano CMOS Emerging Nanotechnology Drivers Emerging Nanotechnology Solutions DNA strands as Bits Molecular orientations as Bits CNFETs SETs Self assembled CNT using DNA Quantum Dots CNT arrays DNA self assembly RTD Molecular Molecules in Solution
  • Computing Devices CMOS Devices Solid State Devices Molecular Devices Nano CMOS Quantum Dot RTD Quantum Devices CNFET SET Electro- mechanical Photoactive Quantum Electro- chemical
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  • Si Nanotransistor(Berkeley Device gp) Hot Spots in Si nanotransistors! Gate Gate Source Drain Nanowire Channel Metallic Carbon Nanotubes: Conducting Wires Semiconducting Nanotubes: Transistors nano-scale circuits ! 1 nm transistor!
  • Nanotubes/wires: CNT DNA Inorganic  Si, Cu, vanadium oxide , Thermal conductivity ~ 3000 W / mK in the axial direction with small values in the radial direction & Very high current carrying capacity
  • Current focus is to grow 1-d nanowires Motivation • One-dimensional quantum confinement • Bandgap varies with wire diameter • Single crystal with well-defined surface structural properties • Tunable electronic properties by doping • Truly bottom-up integration possible Various Inorganic Nanowires Down to 0.4 eV
  • Electrical interconnects Copper, Tungsten Photonics (Q-switch, blue-green laser diode, blue-UV photodetector) Zinc Selenide Electronics, optoelectronics Indium Phosphide Insulator Boron Nitride High temperature electronics, UV detectors and lasers, automotive electronics and sensors Wide Bandgap Nitrides (GaN) Field emission device Copper Oxide UV laser, field emission device, chemical sensor Zinc Oxide Transparent conductive film in display electrodes, solar cells, organic light emitting diodes Indium Tin Oxide Chemical sensors, biosensors Indium Oxide Chemical sensors Tin Oxide Electronics, IR detectors Germanium Electronics, sensors Silicon APPLICATION MATERIAL
  • Nanotube Logic Circuits (Logic Gate Implementation using nanoCMOS) Nanotube Logic (Avouris et al ., IBM) What next ???
  • Can we scale down further ???
  • Computing Devices CMOS Devices Solid State Devices Molecular Devices Nano CMOS Quantum Dot RTD Quantum Devices CNFET SET Electro- mechanical Photoactive Quantum Electro- chemical
  • Molecular Electronics
    • Incentives
        • Molecules are nano-scale
        • Self assembly is achievable
        • Very low-power operation
        • Highly uniform devices
    • Quantum Effect Devices
        • Building quantum wells using molecules
    • Electromechanical Devices
        • Using mechanical switching of atoms or molecules
    • Electrochemical Devices
        • Chemical interactions to change shape or orientation
    • Photoactive Devices
        • Light frequency changes shape and orientation.
  • Molecular Electronics
    • Mechanical synthesis
        • Molecules aligned using a scanning tunneling microscope (STM)
        • Fabrication done molecule by molecule using STM
    • Chemical synthesis
        • Molecules aligned in place by chemical interactions
        • Self assembly
        • Parallel fabrication
    Benzene ring Acetylene linkage Thiol
  • An Atomic Relay
  • Summary and Challenges
    • Summary
        • Parallel self assembly
        • Very regular structures
        • Many alternatives proposed but inherent problems
        • Very low energy operation
    • Challenges
        • Signal restoration and gain
        • Finding non-interacting chemicals
        • Chemical reactions stochastic with by-products
        • Slow operating speeds
    • Open Problems
        • Self assembling of devices
        • Increased speed of operation
        • Guaranteed switching of molecules (HP- UCLA devices)
        • Simulation models and CAD
  • (001)
  • THANK YOU :-) [email_address]
  • Conclusion
    • CMOS technology is approaching saturation – problems in the nanometer range
    • Several new possibilities emerging
      • Carbon nanotubes (CNT)
      • Single-electron transistor (SET) and quantum dots (QD)
      • Molecular computing devices
  • Circuit Fabrication
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  • Fabrication: Imprint Lithography
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    • • Electronic properties are independent of helicity and the number of layers
    • • Applications: Nanoelectronic devices, composites
    • • Techniques: Arc discharge, laser ablation
    • • Also: B2O3 + C (CNT) + N2  2 BN (nanotubes) + 3 CO
  • TubeFET (McEuen et al ., Berkeley)
  • Carbon Nanotube FET
    • CNT can be used as the conducting channel of a MOSFET.
    • These new devices are very similar to the CMOS FETs.
    • All CNFETs are pFETs by nature.
    • nFETs can be made through
        • Annealing
        • Doping
    • Very low current and power consumption
    • Although tubes are 3nm thick CNFETs are still the size of the contacts, about 20nm.
    Courtesy: IBM
  • CNT Fabrication
    • Controlling the conductivity of the tubes (Constructive Destruction)
        • All tubes laid on the contact
        • Metallic tubes are destroyed
    • Controlling diameter of the tube
        • Start with MWNTs.
        • Destroy the outer layers one by one to reduce diameter.
    • Placing exactly at the required location. Yet to be demonstrated convincingly to exploit complete advantage using Lithography.
    • Using DNA for self assembly
        • Demonstrated by Techion-Israel very recently (Nov’2003).
    Courtesy: IBM Courtesy: IBM
  • Summary and Challenges
    • CNTs are flexible tubes that can be made conducting or semiconducting.
    • Nano-scale, strong and flexible.
    • Challenges:
        • Multilevel interconnects not available
        • Chip density still limited to the density of contacts.
        • Tube density not entirely exploited
        • Fabrication is still a stochastic process
        • Alternatives to gold contacts need to be found.
    • Open Problems and Initiatives:
        • Fabrication using DNA for self assembly (Technion-Israel; Science, Nov 2003)
        • Memory array of nanotubes using junctions as bit storages (Lieber at Harvard)
        • Using nanotube arrays to make computing elements (DeHon at Caltech)
        • Fabricate FPGAs using CNFETs and STM (Avouris at IBM)
  • Solid State Quantum Devices
    • Quantum effects used to build devices.
    • Electrons confined on an island
        • Island can be created by using different band-gap devices in succession
        • Island has certain allowed energy levels
        • If allowed energy levels are filled then the device is in conduction
    • Types of devices
        • Resonant Tunneling Diode (RTD)
        • Single Electron Transistor (SET)
        • Quantum Dot (QD)
    • Blocking conduction due to unavailable energy levels is called coulomb blockade
    Energy Occupied Energy Levels Occupied Energy Levels Allowed Energy Levels Source Island Drain Barrier Distance Barrier
  • Principle of Conduction
    • Conduction can occur by
        • Increasing source to drain voltage
        • Applying Gate Bias
    Allowed Energy Levels Source Island Drain Energy Occupied Conduction Band Allowed Energy Levels Source Island Drain Energy Occupied Conduction Band Gate bias Occupied Conduction Band Conduction Conduction
  • Single Electron Transistors (SET)
    • Conductance changes in spurts as energy levels are discrete
    • To go from conducting to non-conducting stage, it requires voltage sufficient for one electron to cross
        • This is achieved by applying gate bias enough for just one electron charge -- hence the name SET
        • Bias required for conduction is coulomb gap voltage
    • Same device can act as pFET or nFET based on the barrier strength
    • Applications:
        • Extra sensitive charge meters
        • CMOS style conducting devices
    Drain Source Gate C g Island
  • Quantum Dots and Arrays
    • 3-dimensional island tunneling barrier
    • State determined by presence of electron and not by conduction.
    • Quantum cell array (QCA) is a lattice of these cells with 2 electrons confined.
    • Occupied electrons are furthest from each other due to repulsive forces.
    Courtesy: vortex.tn.tudelft.nl / grkouwen/kouwen.html Inter-dot Barriers Outer Barriers Dot occupied by Electron Dot unoccupied
  • Quantum Cellular Automata
    • 2 states – “1” and “0”.
    • Electrostatic interaction of nearby cells makes the bits flip.
    • Input to the cell is by manipulating the Inter-dot barriers.
    • Logic gates can be constructed.
    “ 1” “ 0” 1 1 QCA Wire 1 0 QCA Inverter Stable Unstable
  • Summary and Challenges
    • Summary
        • Electrons confined on an island.
        • Allowed energy levels are discrete and allow the device to fluctuate between conducting and non-conducting states.
        • SET – 2 dimensional device with gate bias control.
        • QD – device with electron presence as state.
        • QCA – Arrays of QDs used for computing.
    • Challenges
        • Background charge may offset states (noise sensitivity)
        • Sensitivity of tunneling current to barrier width (lithographic accuracy)
        • Sensitivity to barrier widths
        • Cryogenic operation
    • Open Problems
        • Lithographic methods with guaranteed accuracy
        • Self assembly of systems
        • Background charge elimination
        • Synthesis and verification techniques needed
        • Testing of these devices as stuck-at models may be inadequate.
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